X76F641AEG-2.0 [ICMIC]
Secure Serial Flash; 安全串行闪存
| 型号： | X76F641AEG-2.0 |
| 厂家： | 
IC MICROSYSTEMS |
| 描述： | Secure Serial Flash |
| 文件： | 总17页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
ICmic
8Kx8 + 32x8
This X76F641 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
IC MICROSYSTEMS
64K
X76F641
Secure Serial Flash
FEATURES
DESCRIPTION
•64-bit Password Security
—Five 64-bit Passwords for Read, Program
and Reset
•8192 Byte+32 Byte Password Protected Arrays
—Seperate Read Passwords
—Seperate Write Passwords
—Reset Password
The X76F641 is a Password Access Security Supervisor,
containing one 65536-bit Secure Serial Flash array and
one 256-bit Secure Serial Flash array. Access to each
memory array is controlled by five 64-bit passwords
each. These passwords protect read and write opera-
tions of the memory array. A separate RESET password
is used to reset the passwords and clear the memory
arrays in the event the read and write passwords are lost.
•Programmable Passwords
•Retry Counter Register
The X76F641 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA).
—Allows 8 tries before clearing of both arrays
—Password Protected Reset
•32-bit Response to Reset (RST Input)
•32 byte Sector Program
•400kHz Clock Rate
•2 wire Serial Interface
•Low Power CMOS
The X76F641 also features a synchronous response to reset
providing an automatic output of a hard-wired 32-bit
data stream conforming to the industry standard for
memory cards.
—2.0 to 5.5V operation
—Standby current Less than 1µA
—Active current less than 3 mA
•High Reliability Endurance:
—100,000 Write Cycles
•Data Retention: 100 years
•Available in:
TM
The X76F641 utilizes Xicor’s proprietary Direct Write cell,
providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
—8 lead EIAJ SOIC
—SmartCard Module
Functional Diagram
8K BYTE
SerialFlash ARRAY
ARRAY 0
(PASSWORD PROTECTED)
DATA TRANSFER
SCL
SDA
ARRAY ACCESS
ENABLE
INTERFACE
LOGIC
32 BYTE
SerialFlash ARRAY
ARRAY 1
PASSWORD ARRAY
AND PASSWORD
VERIFICATION LOGIC
(PASSWORD PROTECTED)
RST
RETRY COUNTER
RESET
RESPONSE REGISTER
7025 FM 01
∧Xicor, Inc. 1994, 1995, 1996 Patents
Pending 9900-5004.5 3/9/99 EP
Characteristics subject to change without notice
1
X76F641
PIN DESCRIPTIONS
PIN NAMES
Symbol
SDA
SCL
RST
Vcc
Description
Serial Data Input/Output
Serial Clock Input
Reset Input
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a true three state serial data input/output pin. During
a read cycle, data is shifted out on this pin. During a
write cycle, data is shifted in on this pin. In all
other cases, this pin is in a high impedance state.
Supply Voltage
Ground
Vss
NC
No Connect
Reset (RST)
RST is a device reset pin. When RST is pulsed high the
X76F641 will output 32 bits of fixed data which conforms
PIN CONFIGURATION
to the standard for “synchronous response to reset”.
The part
Smart Card
must not be in a write cycle for the response to reset to
occur. See Figure 11. If there is power interrupted dur-
ing the Response to Reset, the response to reset will be
aborted and the part will return to the standby state. The
response to reset is "mask programmable" only!
EIAJ SOIC
VSS
VCC
1
2
8
7
6
5
NC
SDA
NC
RST
DEVICE OPERATION
3
4
SCL
NC
There are two primary modes of operation for
the X76F641; Protected READ and protected WRITE.
Protected operations must be performed with one of four
8-byte passwords.
GND
VCC
RST
NC
SCL
NC
SDA
NC
The basic method of communication for the device is
generating a start condition, then transmitting a com-
mand, followed by the correct password. All parts will be
shipped from the factory with all passwords equal to ‘0’.
The user must perform ACK Polling to determine the
validity of the password, before starting a data transfer
(see Acknowledge Polling.) Only after the correct pass-
word is accepted and a ACK polling has been performed,
can the data transfer occur.
7025 FM 02
After each transaction is completed, the X76F641 will
reset and enter into a standby mode. This will also be the
response if an unsuccessful attempt is made to access a
protected array.
To ensure the correct communication, RST must remain
LOW under all conditions except when running a
“Response to Reset sequence”.
Data is transferred in 8-bit segments, with each transfer being
followed by an ACK, generated by the receiving
device.
If the X76F641 is in a nonvolatile write cycle a “no A
CK”
(SDA=High) response will be issued in response to loading
of the command byte. If a stop is issued prior to the
nonvolatile write cycle the write operation will be terminated
and the part will reset and enter into a standby
mode.
The basic sequence is illustrated in Figure 1.
2
X76F641
Figure 1. X76F641 Device Operation
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F641 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition is met.
LOAD COMMAND BYTE
LOAD 8-BYTE
PASSWORD
A start may be issued to terminate the input of a control
byte or the input data to be written. This will reset the
device and leave it ready to begin a new read or write
command. Because of the push/pull output, a start can-
not be generated while the part is outputting data. Starts are
inhibited while a write is in progress.
VERIFY PASSWORD
ACCEPTANCE BY
USE OF PASSWORD ACK POLLING
Stop Condition
LOAD 2 BYTE ADDRESS
All communications must be terminated by a stop condi-
tion. The stop condition is a LOW to HIGH transition of
SDA when SCL is HIGH. The stop condition is also used to
reset the device during a command or data input
sequence and will leave the device in the standby power
mode. As with starts, stops are inhibited when outputting
data and while a write is in progress.
READ/WRITE
DATA BYTES
Twc OR DATA ACK POLLING
Acknowledge
7025 FM 03
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received the
eight bits of data.
Retry Counter
The X76F641 contains a retry counter. The retry counter
allows 8 accesses with an invalid password before any
action is taken. The counter will increment with any com-
bination of incorrect passwords. If the retry counter over-
flows, all memory areas are cleared and the device is
locked by preventing any read or write array password
matches. The passwords are unaffected. If a correct
password is received prior to retry counter overflow, the
retry counter is reset and access is granted. In order to
reset the operation of a locked up device, a special reset
command must be used with a RESET password.
The X76F641 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F641 will respond with an acknowledge
after the receipt of each subsequent eight-bit word.
Reset Device Command
The reset device command is used to clear the retry
counter and reactivate the device. When the reset device
command is used prior to the retry counter overflow, the retry
counter is reset and no arrays or passwords are
affected. If the retry counter has overflowed, all memory
areas are cleared and all commands are blocked and the
retry counter is disabled. Issuing a valid reset device
command (with reset password) to the device resets and
re-enables the retry counter and re-enables the other
commands. Again, the passwords are not affected.
Device Protocol
The X76F641 supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as a
receiver. The device controlling the transfer is a master
and the device being controlled is the slave. The master will
always initiate data transfers and provide the clock for
both transmit and receive operations. Therefore, the
X76F641 will be considered a slave in all applications.
Reset Password Command
Clock and Data Conventions
A reset password command will clear both arrays and set all
passwords to all zero.
Data states on the SDA line can change only during SCL
LOW. SDA changes during SCL HIGH are reserved for
indicating start and stop conditions. Refer to Figure 2 and
Figure 3.
3
X76F641
Figure 2. Data Validity
SCL
SDA
Data Stable
Data
Change
7025 FM 04
Figure 3. Definition of Start and Stop Conditions
SCL
SDA
Start Condition
Stop Condition
7025 FM 05
Table 1. X76F641 Instruction Set
1st Byte
after
Password
2nd Byte
after
Password
1st Byte
after Start
Password
used
Read 0
Read 1
Write 0
Write 1
Read 0
Read 1
Write 0
Write 1
Reset
Command Description
Read (Array 0)
1000 0000 High Address Low address
1000 1000 High Address Low address
1001 0000 High Address Low address
1001 1000 High Address Low address
Read (Array 1)
Sector Write (Array 0)
Sector Write (Array 1)
1010 0000
1010 1000
1011 0000
1011 1000
1100 0000
1110 0000
1110 1000
1111 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
not used
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
not used
Change Read 0 Password
Change Read 1 Password
Change Write 0 Password
Change Write 1 Password
Change Reset Password
Reset Password Command
Reset Device Command
ACK Polling command (Ends Password operation)
Reserved
Reset
not used
not used
Reset
not used
not used
None
All the rest
7025 FM T04
Notes:Illegal command codes will be disregarded. The part will respond with a “noC-KA” to the illegal byte and then return to the standby mode.
All write/read operations require a password.
4
X76F641
PROGRAM OPERATIONS
Sector Programming
The sector program mode requires issuing the 8-bit write
command followed by the password, password Ack
command, the address and then the data bytes trans-
ferred as illustrated in figure 4. Up to 32 bytes may be
transferred. After the last byte to be transferred is
acknowledged a stop condition is issued which starts the
nonvolatile write cycle.
Figure 4. Sector Programming
Write
Password
Write
Password
0
Wait tWC
OR
COMMAND
7
Repeated
ACK Polling
Command
SDA
S
If ACK, Then
Password Matches
ACK POLLING
COMMAND
Data 0
. . .
S
Data 31
Wait tWC Data
ACK Polling
S
7025 FM 07
5
X76F641
requires the master to perform an ACK polling with the
specific code of F0h. As with regular Acknowledge polling
the user can either time out for 10ms, and then issue the ACK
polling once, or continuously loop as described in
the flow.
ACK Polling
Once a stop condition is issued to indicate the end of the
host’s write sequence, the X76F641 initiates the internal
nonvolatile write cycle. In order to take advantage of the
typical 5ms write cycle, ACK polling can begin
immediately. This involves issuing the start condition
followed by the new command code of 8 bits (1st byte of
the protocol.) If the X76F641 is still busy with the non
Password ACK Polling Sequence
PASSWORD LOAD
COMPLETED
ENTER ACK POLLING
volatile write operation, it will issue a “no-A
CK” in
response. If the nonvolatile write operation has completed,
an “ACK” will be returned and the host can
then proceed with the rest of the protocol.
ISSUE START
Data ACK Polling Sequence
WRITE SEQUENCE
COMPLETED
ENTER ACK POLLING
ISSUE
PASSWORD
ACK COMMAND
ISSUE START
NO
ACK
RETURNED?
ISSUE NEW
COMMAND
CODE
YES
PROCEED
NO
ACK
RETURNED?
7025 FM 09
If the password that was inserted was correct, then an
“ACK” will be returned once the nonvolatile cycle is over,
in response to the ACK polling cycle immediately following
it.
YES
PROCEED
7025 FM 08
If the password that was inserted was incorrect, then a
“no A
CK” will be returned even if the nonvolatile cycle is
over. Therefore, the user cannot be certain that the pass-
word is incorrect until the 10ms write cycle time has
elapsed.
After the password sequence, there is always a nonvolatile
write cycle. This is done to discourage random
guesses of the password if the device is being tampered
with. In order to continue the transaction, the
X76F641
6
X76F641
Figure 5. Acknowledge Polling
8th clk.
SCL
of 8th
‘ACK’
clk
‘ACK’
clk
8th
clk
pwd. byte
SDA
8th bit
‘ACK’
ACK or
no ACK
START
condition
7025 FM 10
READ OPERATIONS
Sequential Read
The host can read sequentially within an array after the
password acceptance sequence. The data output is
sequential, with the data from address n followed by the data
from n+1. The address counter for read operations
increments all address bits, allowing the entire memory
array contents to be serially read during one operation. At
the end of the address space (address 1FFFh for array 0,
Read operations are initiated in the same manner as write
operations but with a different command code.
Random Read
The master issues the start condition and a Read instruc-
tion and password, performs a Password Ack Polling, then
issues the word address. Once the password has been
acknowledged and first byte has been read, another start
can be issued followed by a new 8-bit address. Random
reads are allowed, but only the low order 8 bits can
change. This limits random reads to a 256 byte block.
Therefore, with a single password cycle only a 256 byte
block of array 0 may be accessed randomly. To randomly
access another block of array 0, a stop must be issued fol-
lowed by a new command/address/password sequence.
A random read of the array 1 can access all locations with-
out another password command sequence.
1Fh for array 1), the counter “rolls o
ver” to address 0 and the
X76F641 continues to output data for each acknowl- edge
received. Refer to figure 7 for the address, acknowledge
edge and data transfer sequence. An acknowledge must
follow each 8-bit data transfer. After the last bit has been
read, a stop condition is generated without a preceding
acknowledge.
Figure 6. Random Read
Read
Password
Read
Password
7
Wait tWC
OR
COMMAND
0
Repeated
ACK Polling
Command
SDA
S
If ACK, then
Password Matches
ACK POLLING
COMMAND
S
S
S
Data Y
Data X
7025 FM 11
7
X76F641
Figure 7. Sequential Read
Read
Password
7
Read
Password
0
Wait tWC
OR
COMMAND
Repeated
ACK Polling
Command
SDA
S
If ACK, then
Password Matches
ACK POLLING
COMMAND
S
S
Data X
Data 0
7025 FM 12
PASSWORDS
After this time, it cannot be determined if the password
has been loaded correctly, without trying the new pass-
word. To determine if the new password has been loaded
correctly the data ACK polling command is issued imme-
diately following the stop bit. If it returns an ACK, then the
two passes of the new password entry do not match. If it
returns a "no ACK" then the passwords match and a high
voltage cycle is in progress. The high voltage cycle is
complete when a subsequent data ACK command
returns an "ACK".
The sequence in Figure 8 shows how to change (pro-
gram) the passwords. The programming of passwords is
done twice prior to the nonvolatile write cycle in order to
verify that the new password is consistent. After the eight
bytes are entered in the second pass, a comparison
takes place. A mismatch will cause the part to reset and
enter into the standby mode.
Data ACK polling can be used to determine if a password
has been loaded correctly, however the data ACK com-
mand must be issued less than 2ms after the stop bit.
There is no way to read any of the passwords.
Figure 8. Change Passwords
Old
Password
Old
Password
Wait tWC
OR
COMMAND
7
0
Repeated
ACK Polling
Command
SDA
S
If ACK, then
Password Matches
New
Password
7
ACK POLLING
COMMAND
Two bytes of “0”
S
Data ACK
Polling
New
Password
New
Password
0
Password
0
7
If immediate ACK,
then New Password error
S
If immediate NACK,
followed by ACK after ~5ms
then New Password OK
7025 FM 13
8
X76F641
Figure 9. Reset Password
Wait tWC
OR
Repeated
ACK Polling
Command
If ACK, then
Device reset
Reset
Password
0
Reset
Password
7
ACK POLLING
COMMAND
Reset Password
COMMAND
SDA
S
S
S
7025 FM 14
Figure 10. Reset Device
Wait tWC
OR
Repeated
ACK Polling
Command
If ACK, then
Device reset
Reset
Password
0
Reset
Password
7
ACK POLLING
COMMAND
Reset Device
COMMAND
SDA
S
S
S
7025 FM 15
is pulsed HIGH and the CLK is within the RST pulse
(meet the t spec.) in the middle of an ISO transaction,
RESPONSE TO RESET (DEFAULT = 19 41 AA 55)
NOL
The ISO Response to reset is controlled by the RST and
CLK pins. When RST is pulsed high during a clock pulse,
the device will output 32 bits of data, one bit per clock,
and it resets to the standby state. This conforms to the
ISO standard for “synchronous response to reset”.
The part
must not be in a write cycle for the response to reset to
occur.
it will output the 32 bit sequence again (starting at bit 0).
Otherwise, this aborts the ISO operation and the part
returns to standby state. If the RST is pulsed HIGH and the
CLK is outside the RST pulse (in the middle of an
ISO transaction), this aborts the ISO operation and the
part returns to standby state.
If there is power interrupted during the Response to
Reset, the response to reset will be aborted and the part
will return to the standby state. A Response to Reset is not
available during a nonvolatile write cycle.
After initiating a nonvolatile write cycle the RST pin must
not be pulsed until the nonvolatile write cycle is complete.
If not, the ISO response will not be activated. If the RST
9
X76F641
Figure 11. Response to RESET (RST)
RST
SCK
0
0
1
0
1
0
00
1
1
0
1
0
1
1
0
10
0
0
1
0000
0
0
1
11
0
1
SO
MSB
LSB
LSB
MSB LSB
MSB
MSB
LSB
2
3
Byte
0
1
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias.....................–. 65°C to +135°C
Storage Temperature..........................–.65°C to +150°C
Voltage on any Pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of the
device at these or any other conditions above those
Respect to V
....................................–..1V to +7V
SS
D.C. Output Curren.t..............................................5..m. A
Lead Temperature
(Soldering, 10 seconds.)...............................3.00°C
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Extended
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
X76F641
Limits
4.5V to 5.5V
2.0V to 3.6V
–20°C
X76F641 – 2.0
7025 FM T05
7025 FM T06
10
X76F641
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz, SDA =
Open
RST = VSS
VCC Supply Current
(Read)
ICC1
1
mA
fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz, SDA =
Open
RST = VSS
VCC Supply Current
(Write)
(3)
ICC2
3
mA
VIL = VCC x 0.1, VIH = VCC x 0.9 fSCL
= 400 KHz, fSDA = 400 KHz
VCC Supply Current
(Standby)
(1)
ISB1
50
1
µA
µA
VSDA = VSCC = VCC Other =
GND or VCC–0.3V
VCC Supply Current
(Standby)
(1)
ISB2
ILI
VIN = VSS to VCC
VOUT = VSS to VCC
VCC = 5.5V
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
ILO
(2)
VCC x 0.3
VIL1
–0.5
(2)
VCC x 0.7VCC + 0.5
VCC x 0.1
VCC = 5.5V
VCC = 2.0V
VCC = 2.0V
VIH1
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
V
V
V
V
(2)
VIL2
–0.5
(2)
VCC x 0.9VCC + 0.5
0.4
VIH2
VOL
IOL = 3mA
7002 FM T07
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
CC
A
Symbol
Test
Max.
Units
Conditions
(3)
VI/O = 0V
COUT
Output Capacitance (SDA)
8
6
pF
(3)
VIN = 0V
CIN
Input Capacitance (RST, SCL)
pF
7002 FM T08
NOTES:
(1) Must perform a stop command after a read command prior to measurement
VIL min. and VIH max. are for reference only and are not tested.
(2)
(3) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
VCC x 0.1 to VCC x 0.9
Input Pulse Levels
5V
3V
Input Rise and Fall Times
Input and Output Timing Level
Output Load
10ns
1533Ο
1.3KΟ
VCC x 0.5
OUTPUT
OUTPUT
100pF
100pF
100pF
7002 FM T09
7025 FM 17
11
X76F641
AC CHARACTERISTICS
AC Specifications (Over the recommended operating conditions)
(1)
Typ
Symbol
fSCL
Parameter
SCL Clock Frequency
Min
Max
Units
0
400
KHz
Pulse width of spikes which must be suppressed by the
input filter
(1)
tIN
50
0.1
1.3
100
ns
∝s
tAA
SCL LOW to SDA Data Out Valid
0.3
0.9
Time the bus must be free before a new transmit
can start
∝s
tBUF
∝s
∝s
∝s
∝s
tLOW
Clock LOW Time
1.3
0.6
0.6
0.6
100
0
tHIGH
Clock HIGH Time
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
ns
∝s
Data In Hold Time
∝s
ns
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
0.6
50
300
(2)
(2)
tR
20 + 0.1 x Cb
20 + 0.1 x Cb
300
300
400
ns
tF
SDA and SCL Fall Time
ns
fSCL_RST
SCL Clock Frequency during Response to Reset
kHz
ns
tSR
Device Select to RST active
200
500
2.25
1.25
1.25
1.25
0
tNOL
RST to SCL Non-Overlap
ns
∝s
tRST
RST High Time
∝s
∝s
∝s
tSU:RST
tLOW_RST
tHIGH_RST
tRDV
Response to Reset Setup Time
Clock LOW during Response to Reset
Clock HIGH during Response to Reset
RST LOW to SDA Valid During Response to Reset
CLK LOW to SDA Valid During Response to Reset
Device Deselect to SDA high impedance
500
500
500
ns
ns
ns
tCDV
0
tDHZ
0
Notes:1. Typical values are for TA = 25˚C and VCC = 5.0V
Notes:2. Cb = Total Capacitance of one bus line in pf.
7025 FM T14
12
X76F641
RESET AC SPECIFICATIONS
Power Up Timing
(2)
Symbol
Parameter
Min.
Typ
Max.
Units
(1)
tPUR
Time from Power Up to Read
Time from Power Up to Write
1
mS
(1)
tPUW
5
mS
7025 FM T11
Notes:1.
2.
Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are periodically
sampled and not 100% tested.
Typical values are for TA = 25˚C and VCC = 5.0V
Nonvolatile Write Cycle Timing
Symbol
Parameter
Write Cycle Time
Min.
Typ.(1)
Max.
Units
(1)
tWC
5
10
mS
7025 FM T12
Notes:1.
tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
TIMING DIAGRAMS
Bus Timing
tR
tF
tHIGH
tLOW
SCL
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STA
SDA IN
tAA
tDH
tBUF
SDA OUT
7025 FM 18
Write Cycle Timing
SCL
8th bit of last byte
ACK
SDA
tWC
Stop
Condition
Start
Condition
7025 FM 19
13
X76F641
RST Timing Diagram – Response to a Synchronous Reset
RST
tRST
tHIGH_RST
tNOL
tNOL
1st
clk
pulse
2nd
clk
pulse
3rd
clk
pulse
CLK
I/O
tLOW_RST
tSU:RST
tCDV
tRDV
DATA BIT (2)
DATA BIT (1)
RST
CLK
I/O
DATA BIT (N+1)
(N+2)
DATA BIT (N)
7025 FM 21
GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS
100
V
CCMAX
= ---------------=----1-.-8--K--Ο-
OLMIN
80
60
40
20
R
I
MIN
R
MAX
t
R
= ----------------
BUS
R
MAX
-
C
R
MIN
20
40 60 80 100
tR = maximum allowable SDA rise time
Bus capacitance in pF
7025 FM 22
14
X76F641
8-LEAD PLASTIC, 0.200” WIDE SMALL OUTLINE
GULLWING PACKAGE TYP “A” (EIAJ SOIC)
0.020 (.508)
0.012 (.305)
.213 (5.41)
.205 (5.21)
.330 (8.38)
.300 (7.62)
PIN 1 ID
.050 (1.27) BSC
.212 (5.38)
.203 (5.16)
.080 (2.03)
.070 (1.78)
.013 (.330)
.004 (.102)
0
REF
8
.010 (.254)
.007 (.178)
.035 (.889)
.020 (.508)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
7025 FM 24
15
X76F641
8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X
8 CONTACT MODULE
6 CONTACT MODULE
11.4
8
0.15
0.2
1
.
59
1.215
1
1.3
1.3
2.54
2.54
35mm TAPE
35mm TAPE
1.422
REJECT
PUNCH
POSITION
8.82
23.02
35
NOTE: ALL MEASUREMENTS IN MILLIMETERS
16
X76F641
ORDERING INFORMATION
X76F641
P
–V
G
T
V
CC
Limits
Blank = 5V 10%
2.0 = 2.0V to 3.6V
Device
G=RoHS Compliant Lead Free package
Blank = Standard package. Non lead free
Temperature Range
Blank = Commercial = 0°C to +70°C
E = Extended = –20°C to +85°C
Package
A = 8-Lead SOIC (EIAJ)
H = Die in Waffle Packs
W = Die in Wafer Form
X = Smart Card Module
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes
no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and
without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional
patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detec- tion and
correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life sup- port
device or system, or to affect its safety or effectiveness.
17
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