1527G1LF [ICSI]
Video Clock Synthesizer; 视频时钟合成器
| 型号： | 1527G1LF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Video Clock Synthesizer |
| 文件： | 总11页 (文件大小：623K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated Circuit Systems
ICS1527
Video Clock Synthesizer
General Description
Features
• Lead-free packaging (Pb-free)
The ICS1527 is a low-cost, high-performance
frequency generator. It is suited to general purpose
phase controlled clock synthesis as well as
line-locked and genlocked high-resolution video
applications. Using ICS’s advanced low-voltage
CMOS mixed-mode technology, the ICS1527 is an
effective clock synthesizer that supports video
projectors and displays at resolutions from VGA to
beyond XGA.
• Low jitter (typical 27 ps short term jitter)
• LVCMOS single-ended clock outputs
• 60/110 MHz speed grades available
• Uses 3.3 V power supply
• 5 Volt tolerant Inputs (HSYNC, VSYNC)
• Coast (ignore HSYNC) capability via VSYNC pin
2
• Industry standard I C-bus programming interface
The ICS1527 offers single-ended clock outputs to 60
or 110 MHz. The HSYNC_out, and VSYNC_out pins
provide the regenerated versions of the HSYNC and
VSYNC inputs synchronous to the CLK output.
2
• PLL Lock detection via I C or LOCK output pin
• 16-pin TSSOP package
Applications
The advanced PLL uses either its internal
programmable feedback divider or an external divider.
The device is programmed by a standard I2C-bus™
serial interface and is available in a TSSOP16
package.
• Frequency synthesis
• LCD monitors, video projectors and plasma displays
• Genlocking multiple video subsystems
Pin Configuration (16-pin TSSOP)
ICS1527 Functional Diagram
VSSD
SDA
SCL
VSYNC
EXTFB
HSYNC
VDDA
VSSA
VDDD
VSSQ
VSYNC_out
VDDQ
CLK
HSYNC_out
LOCK
I2CADR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
HSYNC
VSYNC
I2C
HSYNC_out
VSYNC_out
ICS1527
CLK
EXTFB
External
Divider
MDS 1527 G
Revision 110905
ICS reserves the right to make changes in the preliminary device data
identified in this publication without notice. ICS advises its customers
to obtain the latest version of all device data to verify that information
being relied upon is current and accurate.
ICS1527 Data Sheet
Section 1 Overview
The ICS1527 has the ability to operate in line-locked
mode with the HSYNC input.
Section 1 Overview
The ICS1527 is a user-programmable,
high-performance general purpose clock generator. It
is intended for graphics system line-locked and
genlocked applications, and provides the clock signals
required by high-performance analog-to-digital
converters.
1.1 Phase-Locked Loop
The phase-locked loop has a very wide input frequency
range (8 kHz to 100 MHz). Not only is the ICS1527 an
excellent, general purpose clock synthesizer, but it is
also capable of line-locked operation. Refer to the
block diagram below.
Figure 1-1 Simplified Block Diagram
VCOD
VCO
HSYNC
CP
CLK
2,4,8,16
PFD
FD
12..4103
EXTFB
VSYNC
HSYNC_out
Flip-flop
VSYNC_out
Flip-flop
Note: Polarity controls and other circuit elements are not shown in above diagram for simplicity
The heart of the ICS1527 is a voltage controlled
oscillator (VCO). The VCO speed is controlled by the
voltage on the loop filter. This voltage will be described
later in this section.
input and the HSYNC_out output aligned.
The input HSYNC and VSYNC can be conditioned by a
high-performance Schmitt-trigger by sharpening the
rising/falling edge.
The VCO’s clock output is first passed through the
VCO Divider (VCOD). The VCOD allows the VCO to
operate at higher speeds than the required output
clock.
The HSYNC_out and VSYNC_out signals are aligned
with the output clock (CLK) via a set of flip flops.
1.2 Output Drivers and Logic Inputs
NOTE: Under normal, locked operation the VCOD has
no effect on the speed of the output clocks, just the
VCO frequency.
The ICS1527 uses low-voltage TTL (LVTTL) inputs and
LVCMOS outputs, operating at the 3.3 V supply
voltage. The LVTTL inputs are 5 V tolerant.
The output of the VCOD is the full speed output
frequency seen on the CLK. This clock is then sent
through the 12-bit internal Feedback Divider (FD). The
feedback divider controls how many clocks are seen
during every cycle of the input reference.
The LVCMOS drive resistive terminations or
transmission lines.
1.3 Automatic Power-On Reset Detection
The Phase Frequency Detector (PFD) then compares
the feedback to the input and controls the filter voltage
by enabling and disabling the charge pump. The
charge pump has programmable current drive and will
source and sink current as appropriate to keep the
The ICS1527 has automatic power-on reset detection
(POR) circuitry and it resets itself if the supply voltage
drops below threshold values. No external connection
to a reset signal is required.
MDS 1527 G
2
Revision 110905
Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201 www.icst.com
ICS1527 Data Sheet
Section 1 Overview
2
1.4 I C Bus Serial Interface
The ICS1527 uses a 5 volt tolerant, industry-standard
2
I C-bus serial interface that runs at either low-speed
(100 kHz) or high-speed (400 kHz). The interface uses
12 word addresses for control and status: one
write-only, eight read/write, and three read-only
addresses.
2
Two ICS1527 devices can sit on the same I C bus,
each selected by the Master according to the state of
the I2CADR pin. The 7 bit device address is 0100110
(binary) when I2CADR is low. The device address is
0100111 (binary) when I2CADR is high. See Section 4,
“Programming”
MDS1527 G
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Revision 110905
Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201 www.icst.com
ICS1527 Data Sheet
Section 2 Pin Descriptions
Section 2 Pin Descriptions
Table 2-1 ICS1527 Pin Descriptions
PIN NO. PIN NAME
TYPE
POWER
IN/OUT
IN
DESCRIPTION
Digital ground
Serial data
COMMENTS
Notes
1
2
VSSD
SDA
2
I C-bus
1
2
3
SCL
Serial clock
I C-bus
1
4
VSYNC
EXTFB
HSYNC
VDDA
VSSA
I2CADR
LOCK
IN
Vertical sync
1 & 2
1 & 2
1 & 2
5
IN
External feedback
Horizontal sync
Analog supply
Analog ground
From External Divider
Clock input to PLL
6
IN
7
POWER
POWER
IN
Power for analog circuitry
8
Ground for analog circuitry
2
2
9
I C device address
Chip I C address select
10
LVCMOS
OUT
Lock
PLL lock
11
12
HSYNC_out
CLK
LVCMOS
OUT
HSYNC output
Pixel clock output
Schmitt-trigger filtered HSYNC
realigned with the output pixel clock
LVCMOS
OUT
LVCMOS driver for full-speed clock
13
14
VDDQ
POWER
Output driver supply
VSYNC output
Power for output drivers
VSYNC_out
LVCMOS
OUT
Schmitt-trigger filtered VSYNC
realigned with the output pixel clock
15
16
VSSQ
VDDD
POWER
POWER
Output driver ground
Digital supply
Ground for output drivers
Power for digital sections
Notes: 1. These LVTTL inputs are 5 V tolerant.
2. Connect to ground if unused.
MDS 1527 G
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Revision 110905
Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201 www.icst.com
ICS1527 Data Sheet
Section 3 Register map summary
Section 3 Register map summary
Word
Reset
Address
Name
Access
Bit Name
Bit#
Value
Description
00h
Input
R / W
CPen
0
1
Charge Pump Enable
Control
0=External Enable via VSYNC, 1=Always Enabled
VSYNC_Pol
1
0
VSYNC Polarity (Charge Pump Enable)
Requires 00h:0=0
0=Coast (charge pump disabled) while VSYNC low,
1=Coast (charge pump disabled) while VSYNC high
HSYNC_Pol
Fbk_Pol
2
3
4
0
0
0
HSYNC Polarity
0=Rising Edge, 1=Falling Edge
External Feedback Polarity
0=Positive Edge, 1=Negative Edge
Fbk_Sel
External Feedback Select
0=Internal Feedback, 1=External
Reserved
EnPLS
5
6
0
1
Reserved
Enable PLL Lock Status Output
0=Disable, 1=Enable
Reserved
ICP0-2
7
0
Reserved
01h
Loop
R / W
0-2
ICP (Charge Pump Current)
Control*
Bit 2,1,0 = {000 =1 µA, 001 = 2 µA, 010 = 4 µA... 110 = 64 µA, 111 =
128 µA}. Increasing the PF Detector Gain makes the loop respond
faster, raising the loop bandwidth. The typical value when using the
internal loop filter is 011.
Reserved
VCOD0-1
3
Reserved
4-5
VCO Divider
Bit 5,4= {00 = ÷2, 01=÷4, 10=÷8, 11=÷16}
Reserved
FBD0-7
6-7
0-7
Reserved
02h
03h
FdBk Div
0*
R / W
R / W
Feedback Divider LSBs (bits 0-7)
FdBk Div
1*
FBD8-11
0-3
Feedback Divider MSBs (bits 8-11)
Divider setting = 12 bit word + 8
Minimum 12 = 000000000100
Maximum 4103 =111111111111
Reserved
Reserved
4-7
0-7
Reserved
04h
05h
Reserved
0
Reserved
Schmitt-
trigger*
R / W
Schmitt
control
0
1
0
Schmitt-trigger control
0=Schmitt-trigger, 1=No Schmitt-trigger
Metal_Rev
1-7
Metal Mask Revision Number
06h
Output
Enables
R / W
Reserved
OE
0
1
0
0
Reserved
Output Enable for CLK, HSYNC_out, VSYNC_out
0=High Impedance (disabled), 1=Enabled
Reserved
2-7
0
Reserved
MDS1527 G
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Revision 110905
Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201 www.icst.com
ICS1527 Data Sheet
Section 3 Register map summary
Word
Address
Reset
Value
Name
Access
Bit Name
Bit#
Description
07h
08h
Reserved
Reserved
Reserved
0-6
7
Reserved
0
0
Part requires a 0 for correct operation
Reset
Write
Reserved
0-7
Writing 5Ah resets part and commits values written to word
addresses 01h-03h and 05h
09-0Fh
10h
Reserved Read
Reserved
Reserved
Chip Rev
0-7
0-7
0-7
Reserved
Reserved
Reserved
Reserved
Chip Ver
Read
11h
Chip Rev Read
01
12h
Rd_Reg
Read
Reserved
PLL_Lock
0
1
N/A
N/A
PLL Lock Status
0=Unlocked, 1=Locked
Reserved
2-7
0
Reserved
*. Written values to these registers do not take effect immediately, but require a commit via register 08h
MDS 1527 G
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Revision 110905
Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201 www.icst.com
ICS1527 Data Sheet
Section 4 Programming
Section 4 Programming
2
4.1 Industry-Standard I C Serial Bus: Data Format
2
Figure 4-1 ICS1527 Data Format for I C 2-Wire Serial Bus
Single/multiple register write (page write)
Device address
Word address
Word address
Data (0)
Data (0)
Data (n)
S
T
A
R
T
0
1
0
0
1
1
B
0
A
C
K
A
C
K
A
C
K
...
A
C
K
S
T
O
P
Single/multiple register read
Device address
Device address
Data (0)
Data (n)
S
T
A
R
T
0
1
0
0
1
1
B
0
A
C
K
A
C
K
S
T
A
R
T
0
1
0
0
1
1
B
1
A
C
K
A
C
K
...
N
O
A
C
K
S
T
O
P
Sequential single/multiple register read
Device address
Data (n)
S
T
A
R
T
0
1
0
0
1
1
B
1
A
C
K
A
C
K
...
N
O
A
C
K
S
T
O
P
Master drives line
Slave drives line
Notes:
The ICS1527 uses 16 byte pages (00h-0Fh is the first page, 10h-1Fh is the second page). Writing or reading
beyond the end of page yields undefined results.
The ICS1527 has a device address of 010011B, where B is the state of the I2CADR pin.
MDS1527 G
7
Revision 110905
Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201 www.icst.com
ICS1527 Data Sheet
Section 5 AC/DC Operating Conditions
Section 5 AC/DC Operating Conditions
5.1 Absolute Maximum Ratings
Table 5-1 lists absolute maximum ratings for the ICS1527. Stresses above these ratings can cause permanent
damage to the device. These ratings, which are standard values for ICS commercially rated parts, are stress ratings
only. Functional operation of the ICS1527 at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
can affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Table 5-1 ICS1527 Absolute Maximum Ratings
Item
Rating
*
VDD, VDDA, VDDQ (measured to VSS)
Digital Inputs
4.3 V
VSS –0.3 V to 5.5 V
VSS -0.3 V to 6.0 V
VSSA –0.3 V to VDDA +0.3 V
VSSQ –0.3 V to VDDQ +0.3 V
–65°C to +150°C
125°C
Analog Inputs
Analog Outputs
Digital Outputs
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
**
ESD Susceptibility*
> 2 KV
*. Measured with respect to VSS. During normal operations, the VDD supply voltage for the ICS1527 must
remain within the recommended operating conditions.
**. Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation.
Table 5-2 Environmental Conditions
Parameter
Min.
0
Typ.
–
Max.
+70
Units
° C
Ambient Operating Temperature
Power Supply Voltage
+3.0
+3.3
+3.6
V
Table 5-3 DC Characteristics
Parameter
Symbol
IDDD
Conditions
Min.
Max.
25
UNITS
mA
Digital Supply Current
VDDD = 3.6 V
-
-
Output Driver Supply Current
IDDQ
VDDD = 3.6 V
6
mA
No drivers enabled
Analog Supply Current
Power consumption
IDDA
VDDA = 3.6 V
VSS
-
5
mA
mW
V
300
1.8
Power-On-Reset (POR)
Threshold
MDS 1527 G
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Revision 110905
Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201 www.icst.com
ICS1527 Data Sheet
Section 5 AC/DC Operating Conditions
Table 5-4 AC Characteristics
Parameter
Symbol
Min.
Typical
Max.
Units
Notes
General
VCO Frequency
f
50
400
MHz
VCO
VCO Gain
K
165
MHz/V
AC Inputs
EXTFB Input Frequency
EXTFB Input High Voltage
EXTFB Input Low Voltage
f
8
10,000
2.0
kHz
V
EXTFB
V
IH
V
1.0
V
IL
Analog Input (HSYNC/VSYNC)
HSYNC Input Frequency
VSYNC Input Frequency
Input High Voltage
f
8
30
10,000
120
5.5
kHz
Hz
V
HSYNC
f
VSYNC
V
1.7
IH
Input Low Voltage
V
VSS - 0.3
0.2
1.1
V
IL
Input Hysteresis
0.8
V
Schmitt trigger active
SDA, SCL Digital Inputs
Input High Voltage
V
2
5.5
0.8
V
V
IH
Input Low Voltage
V
VSS - 0.3
IL
2
I CADDR Digital Input
Input High Voltage
V
2
VDD+0.3
0.8
V
V
IH
Input Low Voltage
V
VSS - 0.3
IL
SDA Digital Output
SDA Output Low Voltage
SDA Output High Voltage
V
0.4
6.0
V
V
IOUT = 3 mA
OL
V
Determined by
OH
external Rset resistor
LVCMOS Outputs (CLK, HSYNC_out, VSYNC_out, LOCK)
Output Frequency,
ICS1527-110GLF
F
2.5
2.5
45
110
MHz
MHz
VDDD = 3.3 V
VDDD = 3.3 V
2
s
Output Frequency,
ICS1527-60GLF
F
60
s
Duty Cycle
S
50
55
%
ns
ns
ns
V
DC
Jitter, STJ, RMS
Jitter, STJ, pk-pk
Jitter, Input-Output
Output Low Voltage
Output High Voltage
STJ
STJ
IOJ
0.027
0.200
2.500
30 kHz input to 50
MHz output
HSYNC in to CLK out
IOUT = 4 mA
IOUT = -4 mA
1
V
0.4
9
OL
V
2.4
V
OH
HSYNC to HSYNC_out
propagation delay (without
Schmitt-trigger)
2
ns
MDS1527 G
9
Revision 110905
Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201 www.icst.com
ICS1527 Data Sheet
Section 5 AC/DC Operating Conditions
Parameter
Symbol
Min.
Typical
Max.
Units
Notes
HSYNC to HSYNC_out
propagation delay (with
Schmitt-trigger)
6
10
ns
1
CLK to HSYNC_out/
VSYNC_out skew
1.0
1.5
ns
ns
Clock and
HSYNC_out/VSYNC_out
Transition Time - Rise
T
1.0
1.0
2
2
CR
Clock and
HSYNC_out/VSYNC_out
Transition Time - Fall
T
T
1.5
ns
CF
LOCK Transition Time - Rise
LOCK Transition Time - Fall
3.0
2.0
ns
ns
2
2
LR
T
LF
Note 1—Measured between chosen edge of HSYNC (00h:2) and rising edge of output
o
Note 2—Measured at 110 MHz, 3.3 VDC, 25 C, 15 pF, unterminated
MDS 1527 G
10
Revision 110905
Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201 www.icst.com
ICS1527 Data Sheet
Section 6 Package Outline and Package Dimensions
Section 6 Package Outline and Package Dimensions
16-pin TSSOP 4.40 mm body, 0.65 mm pitch
Package dimensions are kept current with JEDEC Publication No. 95
16
Millimeters
Min Max
Inches
Max
Symbol
Min
--
A
A1
A2
b
--
1.20
0.15
1.05
0.30
0.20
5.1
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E1
E
INDEX
AREA
C
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
D
E
E1
e
6.40 BASIC
4.30 4.50
0.65 Basic
1 2
D
L
α
0.45
0°
0.75
8°
0.018
0°
0.030
8°
aaa
--
0.10
--
0.004
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
aaa C
Section 7 Ordering Information
Part / Order Number
Marking
Shipping
packaging
Package
Temperature
ICS1527G-60LF
ICS1527G-60LFT
ICS1527G-110LF
ICS1527G-110LFT
1527G2LF
1527G2LF
1527G1LF
1527G1LF
Tubes
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
Tape & Reel
Tubes
Tape & Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS1527 G
11
Revision 110905
Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201 www.icst.com
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