26B01 [ICSI]
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER; 低偏移， 1到2差分至LVCMOS / LVTTL扇出缓冲器
| 型号： | 26B01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER |
| 文件： | 总14页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS83026I-01 is a low skew, 1-to-2 Dif- • Two LVCMOS / LVTTL outputs
ICS
HiPerClockS™
ferential-to-LVCMOS/LVTTL Fanout Buffer and
• Differential CLK, nCLK input pair
a member of the HiPerClockS™family of
High Performance Clock Solutions from
ICS. The differential input can accept most dif-
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
ferential signal types (LVPECL, LVDS, LVHSTL, HCSL and
SSTL) and translate to two single-ended LVCMOS/LVTTL out-
puts.The small 8-lead SOIC footprint makes this device ideal
for use in applications with limited board space.
• Maximum output frequency: 350MHz
• Output skew: 15ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• Small 8 lead SOIC package saves board space
• 3.3V core, 3.3V, 2.5V or 1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
VDD
CLK
nCLK
OE
VDDO
Q0
1
2
3
4
8
7
6
5
Q1
GND
Q0
CLK
nCLK
Q1
ICS83026I-01
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
OE
TopView
VDD
CLK
nCLK
OE
VDDO
Q0
1
2
3
4
8
7
6
5
Q1
GND
ICS83026I-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
TopView
83026BMI-01
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REV.A JANUARY 16, 2006
1
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDD
Type
Description
Positive supply pin.
1
2
Power
Input
CLK
Pulldown Non-inverting differential clock input.
Pullup/
3
4
nCLK
OE
Input
Input
Inverting differential clock input. VDD/2 default when left floating.
Pulldown
Output enable. When HIGH, outputs are enabled. When LOW, outputs are in
High Impedance State. LVCMOS / LVTTL interface levels.
Pullup
5
6
7
8
GND
Q1
Power
Output
Output
Power
Power supply ground.
Clock output. LVCMOS / LVTTL interface levels.
Clock output. LVCMOS / LVTTL interface levels.
Output supply pin.
Q0
VDDO
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
VDD, VDDO = 3.465V
17
16
15
pF
pF
pF
kΩ
kΩ
Ω
Power Dissipation Capacitance
(per output)
CPD
VDD = 3.465V, VDDO = 2.625V
VDD = 3.465V, VDDO = 1.95V
RPULLUP
Input Pullup Resistor
51
51
7
RPULLDOWN Input Pulldown Resistor
VDD, VDDO = 3.3V
ROUT
Output Impedance
VDD = 3.3V, VDDO = 2.5V
VDD = 3.3V, VDDO = 1.8V
8
Ω
10
Ω
TABLE 3. CONTROL FUNCTION TABLE
Input
OE
0
Outputs
Q0, Q1
HiZ
1
Active
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REV.A JANUARY 16, 2006
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ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
DD
Inputs, V
-0.ꢀV to VDD + 0.ꢀ V
-0.ꢀV to VDDO + 0.ꢀV
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, VO
PackageThermal Impedance, θ
8 Lead SOIC
JA
112.7°C/W (0 lfpm)
101.7°C/W (0 lfpm)
8 LeadTSSOP
StorageTemperature, T
-6ꢀ°C to 1ꢀ0°C
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V ꢀ5, VDDO = 1.71V TO 3.46ꢀV, TA = -40°C TO 8ꢀ°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
Positive Supply Voltage
3.13ꢀ
3.13ꢀ
2.37ꢀ
1.71
3.3
3.3
2.ꢀ
1.8
3.46ꢀ
3.46ꢀ
2.62ꢀ
1.89
10
V
V
VDDO
Output Supply Voltage
V
V
IDD
Power Supply Current
Output Supply Current
mA
mA
IDDO
3
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V ꢀ5, VDDO = 2.37ꢀV TO 3.46ꢀV, TA = -40°C TO 8ꢀ°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum
Units
V
VIH
VIL
IIH
Input High Voltage OE
Input Low Voltage OE
Input High Current OE
Input Low Current OE
2
VDD + 0.3
-0.3
0.8
ꢀ
V
VDD = VIN = 3.46ꢀV
µA
µA
V
IIL
VDD = 3.46ꢀV, VIN = 0V
-1ꢀ0
2.6
VDDO = 3.13ꢀV
VOH
Output High Voltage; NOTE 1
VDDO = 2.37ꢀV
1.8
V
VOL
Output Low Voltage; NOTE 1
0.ꢀ
V
NOTE 1: Outputs terminated with ꢀ0Ω to VDDO/2. See Parameter Measurement Information section,
"Output Load Test Circuit" diagrams.
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V ꢀ5, VDDO = 1.8V ꢀ5, TA = -40°C TO 8ꢀ°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VDD + 0.3
0.8
Units
V
VIH
VIL
IIH
Input High Voltage OE
Input Low Voltage OE
Input High Current OE
2
-0.3
V
VDD = VIN = 3.46ꢀV
VDD = 3.46ꢀV, VIN = 0V
IOH = -100µA
ꢀ
µA
µA
V
IIL
Input Low Current
OE
-1ꢀ0
VDDO - 0.2
VDDO - 0.4ꢀ
VOH
Output High Voltage
I
OH = -2mA
IOL = 100µA
OL = 2mA
V
0.2
V
VOL
Output Low Voltage
I
0.4ꢀ
V
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REV.A JANUARY 16, 2006
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ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 3D. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.71V TO 3.465V, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VDD = 3.465V
VIN = VDD = 3.465V
IN = 0V, VDD = 3.465V
IN = 0V, VDD = 3.465V
Minimum Typical Maximum Units
nCLK
CLK
150
150
µA
µA
µA
µA
V
nCLK
CLK
V
V
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage; NOTE 1
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 2, 3
GND + 0.5
VDD - 0.85
V
NOTE 1: VPP can exceed 1.3V provided that there is sufficient offset level to keep VIL > 0V.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 3: Common mode voltage is defined as VIH.
TABLE 4A. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
350
2.5
15
MHz
ns
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
IJ 350MHz
1.3
1.9
tsk(o)
tsk(pp)
ps
Part-to-Part Skew; NOTE 3, 4
900
ps
Buffer Additive Phase Jitter, RMS, refer to
Additive Phase Jitter Section
tjit
0.03
ps
tR / tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
IJ 66MHz
150
48
800
52
ps
ꢀ
ꢀ
ꢀ
odc
Output Duty Cycle
67MHz ≤ ƒ≤ 166MHz
45
55
167MHz ≤ ƒ≤ 350MHz
40
60
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 6.
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REV.A JANUARY 16, 2006
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ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
350
Units
MHz
ns
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
IJ 350MHz
1.5
2.0
2.6
tsk(o)
tsk(pp)
15
ps
Part-to-Part Skew; NOTE 3, 4
750
ps
Buffer Additive Phase Jitter,
RMS, refer to Additive Phase
Jitter Section
tjit
0.03
ps
tR / tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
IJ 66MHz
150
48
800
52
ps
ꢀ
ꢀ
ꢀ
odc
Output Duty Cycle
67MHz ≤ ƒ≤ 166MHz
46
54
167MHz ≤ ƒ≤ 350MHz
40
60
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4C. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
350
Units
MHz
ns
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
IJ 350MHz
1.9
2.5
3.1
tsk(o)
tsk(pp)
15
ps
Part-to-Part Skew; NOTE 3, 4
600
ps
Buffer Additive Phase Jitter,
RMS, refer to Additive Phase
Jitter Section
tjit
0.03
ps
tR / tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
IJ 66MHz
200
48
900
52
ps
ꢀ
ꢀ
ꢀ
odc
Output Duty Cycle
67MHz ≤ ƒ≤ 166MHz
43
57
167MHz ≤ ƒ≤ 350MHz
40
60
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83026BMI-01
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REV.A JANUARY 16, 2006
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ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
Input/Output Additive
Phase Jitter at 155.52MHz
= 0.03ps typical
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
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REV.A JANUARY 16, 2006
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ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
2.05V 0.103V
1.25V 5ꢀ
SCOPE
SCOPE
VDD,
VDDO
VDD
VDDO
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3VCORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3VCORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.4 0.125V
0.9V 0.45V
VDD
SCOPE
VDD
nCLK
VDDO
VPP
VCMR
Cross Points
Qx
LVCMOS
CLK
GND
GND
-0.9V 0.45V
3.3VCORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
Qx
VDDO
2
VDDO
Qx
Qy
2
PART 2
Qy
VDDO
VDDO
2
2
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
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ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
nCLK
CLK
80ꢀ
tF
80ꢀ
tR
VDDO
2
Q0, Q1
20ꢀ
20ꢀ
t
Clock
Outputs
PD
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
VDDO
2
Q0, Q1
tPW
tPERIOD
tPW
x 100ꢀ
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV.A JANUARY 16, 2006
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ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating.We recommend
that there is no trace attached.
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ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 2A to 2E show inter- For example in Figure 2A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
SCHEMATIC EXAMPLE
LVCMOS drivers. In this example, series termination approach
is shown. Additional termination approaches are shown in the
LVCMOSTermination Application Note.
Figure 3 shows an application schematic example of ICS83026I-
01. The ICS83026I-01 CLK/nCLK input can directly accepts
various types of differential signal. In this example, the input is
driven by an LVDS driver. The ICS83026I-01 outputs are
VDD
3.3V
R3
1K
VDD
VDDO
Zo = 50 Ohm
1
2
3
4
8
7
6
5
R1
43
VDD
CLK
nCLK
OE
VDDO
Q0
Q1
Zo = 50 Ohm
GND
R4
100
LVCMOS
C2
0.1u
LVDS
U1
ICS83026I-01
C1
Zo = 50 Ohm
0.1u
Zo = 50 Ohm
VDD=3.3V
VDDO= 3.3V, 2.5V or 1.8V
R2
43
LVCMOS
FIGURE 3. ICS83026I-01 SCHEMATIC EXAMPLE
RELIABILITY INFORMATION
TABLE 5A. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θ
JA by Velocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE5B. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θ
JA by Velocity (Linear Feet per Minute)
0
200
90.5°C/W
500
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
TRANSISTOR COUNT
The transistor count for ICS83026I-0I is: 260
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ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC
PACKAGE OUTLINE - G SUFFIX FOR 8 LEADTSSOP
TABLE 6A. PACKAGE DIMENSIONS
TABLE 6B. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Millimeters
SYMBOL
MINIMUM
MAXIMUM
Minimum
Maximum
N
A
A1
B
C
D
E
e
8
N
A
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
1.27 BASIC
E
6.40 BASIC
0.65 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
E1
e
4.30
4.50
L
L
0.45
0°
0.75
8°
α
α
Reference Document: JEDEC Publication 95, MS-012
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
www.icst.com/products/hiperclocks.html
83026BMI-01
REV.A JANUARY 16, 2006
12
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS83026BMI-01
Marking
3026BI01
3026BI01
026BI01L
026BI01L
26B01
Package
8 lead SOIC
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS83026BMI-01T
ICS83026BMI-01LF
ICS83026BMI-01LFT
ICS83026BGI-01
8 lead SOIC
2500 tape & reel
tube
8 lead "Lead-Free" SOIC
8 lead "Lead-Free" SOIC
8 lead TSSOP
2500 tape & reel
tube
ICS83026BGI-01T
ICS83026BGI-01LF
ICS83026BGI-01LFT
26B01
8 lead TSSOP
2500 tape & reel
tube
TBD
8 lead "Lead-Free" TSSOP
8 lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
83026BMI-01
www.icst.com/products/hiperclocks.html
REV.A JANUARY 16, 2006
13
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
1
3
Added 8 Lead TSSOP package to Pin Assignment.
Absolute Maximum Ratings - added 8 Lead TSSOP to Package Thermal
Impedance.
A
6/25/04
11
12
13
Added 8 Lead TSSOP Reliability Information table.
Added 8 Lead TSSOP Package Outline and Package Dimensions.
Ordering Information Table - added 8 Lead TSSOP ordering information.
T7
A
A
6
3
Additive Phase Jitter - corrected X axis on plot.
8/2/05
T3C
LVCMOS DC Characteristics - corrected Test Conditions for IIH and IIL.
8/12/05
1
9
Features Section - added lead-free bullet
Added Recommendations for Unused Output Pins.
A
1/16/06
T7
13
Ordering Information Table - added lead-free part number, marking, and note.
83026BMI-01
www.icst.com/products/hiperclocks.html
REV.A JANUARY 16, 2006
14
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