3011C [ICSI]
FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR; FEMTOCLOCKS -TM CRYSTAL - TO- 3.3V LVPECL时钟发生器
| 型号： | 3011C |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR |
| 文件： | 总11页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS843011C
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS843011C is a Fibre Channel Clock • One differential 3.3V LVPECL output
ICS
HiPerClockS™
Generator and a member of the HiPerClocksTM
family of high performance devices from ICS.
The ICS843011C uses a 26.5625MHz crystal to
synthesize 106.25MHz or a 25MHz crystal to
• Crystal oscillator interface designed for 26.5625MHz
18pF parallel resonant crystal
• Output frequency: 106.25MHz or 100MHz
• VCO range: 560MHz - 680MHz
synthesize 100MHz. The ICS843011C has excellent <1ps
phase jitter performance, over the 637kHz – 10MHz
integration range. The ICS843011C is packaged in a small
8-pin TSSOP, making it ideal for use in systems with limit-
ed board space.
• RMS phase jitter @ 100MHz, using a 25MHz crystal
(637kHz - 10MHz): 0.29ps (typical)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
FREQUENCY TABLE
Crystal (MHz) Output Frequency (MHz)
26.5625
25
106.25
100
BLOCK DIAGRAM
PIN ASSIGNMENT
VCCA
VEE
VCC
Q
1
2
3
4
8
7
6
5
VCO
XTAL_IN
OSC
XTAL_OUT
Q
Phase
Detector
÷6
637.5MHz w/
26.5625MHz Ref.
nQ
XTAL_OUT
XTAL_IN
nQ
nc
ICS843011C
M = ÷24 (fixed)
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843011CG
www.icst.com/products/hiperclocks.html
REV.A JANUARY 25, 2006
1
PRELIMINARY
ICS843011C
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
VCCA
VEE
Type
Description
1
2
Power
Power
Analog supply pin.
Negative supply pin.
3,
4
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Input
5
6, 7
8
nc
nQ, Q
VCC
Unused
Output
Power
No connect.
Differential clock outputs. LVPECL interface levels.
Core supply pin.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
843011CG
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REV.A JANUARY 25, 2006
2
PRELIMINARY
ICS843011C
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
101.7°C/W (0 mps)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
ICCA
IEE
Core Supply Voltage
3.465
3.465
V
Analog Supply Voltage
Analog Supply Current
Power Supply Current
3.135
3.3
V
included in IEE
10
mA
mA
68
TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCC - 1.4
VCC - 2.0
0.6
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
25
Typical Maximum Units
Fundamental
Mode of Oscillation
Frequency
26.5625
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
93.33
113.33
MHz
106.25MHz;
Integration Range: 637kHz - 10MHz
100MHz;
0.29
0.29
ps
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
ps
Integration Range: 637kHz - 10MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
400
50
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plot.
843011CG
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REV.A JANUARY 25, 2006
3
PRELIMINARY
ICS843011C
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
SCOPE
VCC
Qx
Phase Noise Mask
LVPECL
VEE
nQx
Offset Frequency
f1
f2
-1.3V 0.165V
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ
80ꢀ
tF
80ꢀ
tR
Q
VSWING
20ꢀ
tPW
tPERIOD
Clock
Outputs
20ꢀ
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
843011CG
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REV.A JANUARY 25, 2006
4
PRELIMINARY
ICS843011C
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843011C provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC and VCCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843011C has been characterized with 18pF parallel parallel resonant crystal and were chosen to minimize the
resonant crystals. The capacitor values, C1 and C2, shown in ppm error. The optimum C1 and C2 values can be slightly
Figure 2 below were determined using a 26.5625MHz, 18pF adjusted for different board layouts.
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
843011CG
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REV.A JANUARY 25, 2006
5
PRELIMINARY
ICS843011C
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
APPLICATION SCHEMATIC
Figure 3A shows a schematic example of the ICS843011C. generating 106.25MHz output frequency. The C1 = 27pF and
An example of LVEPCL termination is shown in this sche- C2 = 33pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 values may be slightly
matic. Additional LVPECL termination approaches are shown
in the LVPECL Termination Application Note. In this example, adjusted for optimizing frequency accuracy.
an 18 pF parallel resonant 26.5625MHz crystal is used for
VCC
VCCA
VCC
R2
10
C3
10uF
C4
0.1u
R3
R5
133
133
U2
Zo = 50 Ohm
Zo = 50 Ohm
Q
VCC
1
8
7
6
5
VCCA
VEE
XTAL_OUT
XTAL_I N
VCC
Q
nQ
nc
+
-
2
3
4
XTAL_OUT
nQ
C2
33pF
X1
26.5625MHz
18pF
843011C
XTAL_IN
R4
82.5
R6
82.5
C5
0.1u
C1
27pF
Zo = 50 Ohm
Zo = 50 Ohm
Q
+
-
nQ
R5
50
R6
50
R7
50
Optional
Y-Termination
FIGURE 3A. ICS843011C SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of ICS843011C P.C. board lay-
out. The crystal X1 footprint shown in this example allows
installation of either surface mount HC49S or through-hole
HC49 package. The footprints of other components in this
example are listed in the Table 6. There should be at least one
decoupling capacitor per power pin. The decoupling capaci-
tors should be located as close as possible to the power pins.
The layout assumes that the board has clean analog power
ground plane.
TABLE 6. FOOTPRINTTABLE
Reference
C1, C2
C3
Size
0402
0805
0603
0603
C4, C5
R2
NOTE: Table 6, lists component
sizes shown in this layout example.
FIGURE 3B. ICS843011 PC BOARD LAYOUT EXAMPLE
843011CG
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REV.A JANUARY 25, 2006
6
PRELIMINARY
ICS843011C
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843011C.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843011C is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 68mA = 235.6mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 235.6mW + 30mW = 265.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W perTable 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.266W * 90.5°C/W = 109.1°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7.THERMAL RESISTANCE θJA FOR 8-PINTSSOP, FORCED CONVECTION
θ
JA by Velocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
843011CG
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REV.A JANUARY 25, 2006
7
PRELIMINARY
ICS843011C
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT ANDT ERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mWL
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843011CG
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REV.A JANUARY 25, 2006
8
PRELIMINARY
ICS843011C
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TRANSISTOR COUNT
The transistor count for ICS843011C is: 2436
843011CG
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REV.A JANUARY 25, 2006
9
PRELIMINARY
ICS843011C
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843011CG
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REV.A JANUARY 25, 2006
10
PRELIMINARY
ICS843011C
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS843011CG
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
3011C
3011C
TBD
8 lead TSSOP
ICS843011CGT
ICS843011CGLF
ICS843011CGLFT
8 lead TSSOP
2500 tape & reel
tube
8 lead "Lead-Free" TSSOP
8 lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring ehigh reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
843011CG
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REV.A JANUARY 25, 2006
11
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