650R-27ILF [ICSI]
Networking Clock Source; 网络时钟源
| 型号： | 650R-27ILF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Networking Clock Source |
| 文件： | 总6页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS650-27
Networking Clock Source
Description
Features
The ICS650-27 is a low cost, low jitter, high
• Packaged in 20-pin (150 mil) SSOP (QSOP)
• Available in Pb (lead) free package
performance clock synthesizer for networking
applications. Using analog Phase-Locked Loop (PLL)
techniques, the device accepts a 12.5 MHz or 25 MHz
clock or fundamental mode crystal input to produce
multiple output clocks for networking chips, PCI
devices, SDRAM, and ASICs. The ICS650-27 outputs
all have zero ppm synthesis error.
• 12.5 MHz or 25 MHz fundamental crystal or clock
input
• Six output clocks with selectable frequencies
• SDRAM frequencies of 67, 83, 100, and 133 MHz
• Buffered crystal reference output
• Zero ppm synthesis error in all clocks
• Ideal for PMC-Sierra’s ATM switch chips
The ICS650-27 is pin compatible and functionally
equivalent to the ICS650-07. It is a performance
upgrade and is recommended for all new 3.3V
designs.
• Full CMOS output swing with 25 mA output drive
capability at TTL levels
• Advanced, low-power, sub-micron CMOS process
• Operating voltage of 3.3 V
See the MK74CB214, ICS551, and ICS552-01 for
non-PLL buffer devices which produce multiple
low-skew copies of these output clocks.
• Industrial temperature only
See the ICS570, ICS9112-16/17/18 for zero delay
buffers that can synchronize outputs and other needed
clocks.
Block Diagram
VDD
2
CLKA1
2
/2
ACS1:0
CLKA2
2
CLKB1
Clock
BCS1:0
Synthesis
and Control
CLKB2
CCS
/2
Circuitry
CLKC1
CLKC2
X1/ICLK
Clock
Buffer/
Crystal
Oscillator
25 or 12.5 MHz
cyrstal or clock
REFOUT
X2
2
OE (all outputs)
GND
MDS 650-27 D
1
Revision 070505
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS650-27
Networking Clock Source
Pin Assignment
ASC0
X2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
BCS1
BCS0
REFOUT
CLKA1
VDD
X1/ICLK
VDD
ASC1
GND
OE
CLKC1
CLKC2
CLKB2
CLKB1
GND
CLKA2
DC
CCS
20-pin (150 mil) SSOP
Pin Descriptions
Pin
Pin
Pin
Type
Pin Description
Number Name
1
2
ACS0
X2
Input
Input
A clock select 0. Selects outputs on CLKA1 and CLKA2 per table on page 3.
Crystal connection. Connect to a fundamental crystal or leave unconnected for a clock
input.
3
4
5
X1/ICLK
VDD
Input
Crystal connection. Connect to a fundamental crystal or clock input.
Power Connect to +3.3 V or 5 V. Must be the same as pin 16.
ACS1
Input
A clock select 1. Selects outputs on CLKA1 and CLKA2 per table on page 3. Internal
pull-up.
6
GND
CLKC1
CLKC2
CLKB2
CLKB1
CCS
Power Connect to ground.
7
Output Output Clock C1. Depends on setting of CCS per table on page 3.
Output Output Clock C2. Depends on setting of CCS per table on page 3. Same as CLKC1.
Output Output Clock B2. Depends on setting of BCS1, 0 per table on page 3.
Output Output Clock B1. Depends on setting of BCS1, 0 per table on page 3.
8
9
10
11
12
13
14
15
16
17
18
19
20
Input
-
Clock C select pin. Selects outputs on CLKC1 and CLKC2 per table on page 3.
Don’t connect. Do not connect anything to this pin.
DC
CLKA2
GND
Output Output Clock A2. Depends on setting of ACS1, 0 per table on page 3.
Power Connect to ground.
OE
Input
Output enable. Tri-states all outputs when low. Internal pull-up.
VDD
Power Connect to +3.3 V or 5 V. Must be the same as pin 4.
CLKA1
REFOUT
BCS0
BCS1
Output Output Clock A1. Depends on setting of ACS1, 0 per table on page 3.
Output Buffered reference clock output. Same frequency as crystal or clock input.
Input
Input
B clock select 0. Selects outputs on CLKB1 and CLKB2 per table on page 3.
B clock select 1. Selects outputs on CLKB1 and CLKB2 per table on page 3. Internal
pull-up.
MDS 650-27 D
2
Revision 070505
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS650-27
Networking Clock Source
For a 25 MHz fundamental crystal or clock input, the following four tables apply:
A Clocks Select Table (outputs in MHz)
B Clocks Select Table (outputs in MHz)
ASC1
ASC0
CLKA1
100
CLKA2
off (low)
Test
BSC1
BSC0
CLKB1
Test
CLKB2
Test
0
0
0
1
1
1
0
M
1
0
0
0
1
1
1
0
M
1
Test
66.6667
100
33.3333
50
75
off (low)
16.6667
Test
0
33.3333
Test
0
83.3333
Test
41.6667
Test
M
1
M
1
66.6667
33.3333
133.3333
66.6667
C Clocks Select Table (outputs in MHz)
Reference Output Clock Frequency (in MHz)
CCS
0
CLKC1
125
CLKC2
125
REFOUT
25
M
Test
75
Test
75
1
For a 12.5 MHz fundamental crystal or clock input, the following four tables apply:
A Clocks Select Table (outputs in MHz)
B Clocks Select Table (outputs in MHz)
ASC1
ASC0
CLKA1
50
CLKA2
off (low)
Test
BSC1
BSC0
CLKB1
Test
CLKB2
Test
0
0
0
1
1
1
0
M
1
0
0
0
1
1
1
0
M
1
Test
33.3333
50
16.6667
25
37.5
off (low)
8.3333
Test
0
16.6667
Test
0
41.6667
Test
20.8333
Test
M
1
M
1
33.3333
16.6667
66.6667
33.3333
C Clocks Select Table (outputs in MHz)
Reference Output Clock Frequency (in MHz)
CCS
0
CLKC1
62.5
CLKC2
62.5
REFOUT
12.5
M
Test
Test
1
37.5
37.5
0 = connect directly to GND
M = leave unconnected (automatically self biases to VDD/2)
1 = connect directly to VDD
MDS 650-27 D
3
Revision 070505
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS650-27
Networking Clock Source
Crystal Information
External Components
The crystal used should be a fundamental mode (do
not use third overtone), parallel resonant. Crystal
capacitors should be connected from pins X1 to ground
and X2 to ground to optimize the initial accuracy. The
value of these capacitors is given by the following
equation:
The ICS650-27 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
Decoupling capacitors of 0.01µF must be connected
between each VDD and GND (pins 4 and 6, pins 16
and 14), as close to the device as possible. For
optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Crystal caps (pF) = (C - 6) x 2
L
In the equation, C is the crystal load capacitance. So,
L
for a crystal with a 16pF load capacitance, two 20 pF
[(16-6) x 2] capacitors should be used.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be
used. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series
with the clock line as close to the clock output pin as
possible. The nominal impedance of the clock output is
20Ω.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-27. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
-40 to +85°C
-65 to +150°C
175°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+85
Units
°C
Ambient Operating Temperature
-40
Power Supply Voltage (measured in respect to GND)
+3.0
+3.3
+3.6
V
MDS 650-27 D
4
Revision 070505
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS650-27
Networking Clock Source
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
Symbol
VDD
VIH
Conditions
Min.
Typ.
Max.
Units
V
3.0
3.3
3.6
Input High Voltage
X1 pin only, CLK input
X1 pin only, CLK input
all tri-level type inputs
all tri-level type inputs
all other inputs
all other inputs
IOH = -25 mA
VDD/2+1 VDD/2
V
Input Low Voltage
VIL
VDD/2 VDD/2-1
V
Input High Voltage
VIH
VDD-0.5
2
V
Input Low Voltage
VIL
0.5
0.8
0.8
V
Input High Voltage
VIH
V
Input Low Voltage
VIL
V
Output High Voltage
Output Low Voltage
Output High Voltage, CMOS level
Operating Supply Current
Short Circuit Current
Internal pull-up resistor
VOH
VOL
VOH
IDD
2.4
V
IOL = 25mA
V
IOH = -8 mA
VDD-0.4
V
No Load
50
50
mA
mA
kΩ
kΩ
Ω
IOS
Each output
RPU
BCS1, OE pins
ACSI pin
510
120
20
Nominal output impedance
ZOUT
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85°C
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Input Frequency
10
12.5 or
25
27
MHz
Output Rise Time
t
0.8 to 2.0 V, Note 1
2.0 to 0.8 V, Note 1
At VDD/2, Note 1
All clocks
1.5
1.5
60
0
ns
ns
OR
Output Fall Time
t
OF
Output Clock Duty Cycle
Frequency Error
40
50
%
ppm
ps
Absolute Jitter, short term
Variation from mean,
Note 1
150
Note 1: Measured with 15 pF load
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to Ambient
θJA
θJA
θJA
θJC
Still air
135
°C/W
°C/W
°C/W
°C/W
1 m/s air flow
3 m/s air flow
93
78
Thermal Resistance Junction to Case
MDS 650-27 D
60
5
Revision 070505
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS650-27
Networking Clock Source
Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
Min
20
Symbol
A
Min
Max
1.75
0.25
1.50
0.30
0.25
8.75
6.20
4.00
Max
.069
.010
.059
0.012
.010
.344
.244
.157
1.35
0.10
--
0.20
0.18
8.55
5.80
3.80
.053
.0040
--
0.008
.007
.337
.228
.150
A1
A2
b
E1
E
INDEX
AREA
C
D
E
1 2
E1
e
L
0.635 Basic
0.025 Basic
D
0.40
1.27
8°
.016
.050
α
0°
0°
8°
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Tubes
Package
Temperature
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
ICS650R-27I
ICS650R-27IT
ICS650R-27ILF
ICS650R-27ILFT
ICS650R-27I
ICS650R-27I
650R-27ILF
650R-27ILF
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
Tape and Reel
Tubes
Tape and Reel
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result
from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 650-27 D
6
Revision 070505
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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