8304AMI [ICSI]
LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER; 低偏移， 1到4 LVCMOS / LVTTL扇出缓冲器
| 型号： | 8304AMI |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER |
| 文件： | 总12页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8304I
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8304I is a low skew, 1-to-4 Fanout • 4 LVCMOS / LVTTL outputs
,&6
Buffer and a member of the HiPerClockS™
• LVCMOS clock input
HiPerClockS™
family of High Performance Clock Solutions
from ICS. The ICS8304I is characterized at
full 3.3V for input VDD, and mixed 3.3V and
• CLK can accept the following input levels: LVCMOS, LVTTL
• Maximum output frequency: 166MHz
2.5V for output operating supply modes (VDDO). Guaran-
teed output and part-to-part skew characteristics make
the ICS8304I ideal for those clock distribution
applications demanding well defined performance and
repeatability.
• Output skew: 60ps (maximum)
• Part-to-part skew: 650ps (maximum)
• Small 8 lead SOIC package saves board space
• 3.3V input, outputs may be either 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
VDDO
VDD
Q3
Q2
Q1
Q0
1
2
3
4
8
7
6
5
CLK
GND
Q1
CLK
ICS8304I
Q2
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
Q3
M Package
Top View
8304AMI
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REV. B APRIL 4, 2002
1
ICS8304I
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDDO
VDD
Type
Description
1
2
3
4
5
6
7
8
Power
Power
Input
Output supply pin. Connect to 3.3V or 2.5V.
Positive supply pin. Connect to 3.3V.
CLK
GND
Q0
Pulldown LVCMOS / LVTTL clock input.
Power
Output
Output
Output
Output
Power supply ground. Connect to ground.
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
Q1
Q2
Q3
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
pF
Power Dissipation Capacitance
(per output)
CPD
VDD, VDDO = 3.465V
15
RPULLUP
Input Pullup Resistor
51
51
7
KΩ
KΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT
Output Impedance
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ICS8304I
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx
Inputs, VI
4.6V
-0.5V to VDD+ 0.5V
-0.5V to VDDO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
112.7°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
Power Supply Voltage
Output Power Supply Voltage
Power Supply Current
Output Supply Current
3.465
3.465
18
V
VDDO
IDD
3.135
3.3
V
mA
mA
IDDO
11
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VDD + 0.3
1.3
V
V
Input Low Voltage
Input High Current
Input Low Current
-0.3
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
Refer to NOTE 1
IOH = -16mA
150
µA
µA
V
IIL
-5
2.6
2.9
3
VOH
Output High Voltage
Output Low Voltage
V
IOH = -100uA
V
Refer to NOTE 1
IOL = 16mA
0.5
V
VOL
0.25
0.15
V
IOL = 100uA
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Section, "3.3V Output Load Test Circuit".
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REV. B APRIL 4, 2002
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ICS8304I
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
tsk(o)
tsk(pp)
tR
Output Frequency
166
3.3
50
MHz
ns
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
IJ 166MHz
2
f = 133MHz
ps
600
500
500
60
ps
30% to 70%
30% to 70%
250
250
40
ps
tF
Output Fall Time
ps
odc
Output Duty Cycle
%
All parameters measured at 166MHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDO
IDD
Positive Supply Voltage
3.465
2.625
18
V
Output Supply Voltage
Power Supply Current
Output Supply Current
2.375
2.5
V
mA
mA
IDDO
11
TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VDD + 0.3
1.3
V
V
Input Low Voltage
-0.3
Input High Current
VDD = VIN = 3.465V
150
µA
µA
V
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
-5
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
2.1
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Section,
"3.3V/2.5V Output Load Test Circuit".
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ICS8304I
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
tsk(o)
tsk(pp)
tR
Output Frequency
166
3.7
60
MHz
ns
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
IJ 166MHz
2.3
f = 133MHz
ps
650
500
500
60
ps
30% to 70%
30% to 70%
250
250
40
ps
tF
Output Fall Time
ps
odc
Output Duty Cycle
%
All parameters measured at 166MHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8304AMI
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REV. B APRIL 4, 2002
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ICS8304I
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
SCOPE
VDD,
VDDO
Qx
LVCMOS
GND
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
1.25V±5%
2.05V±5%
SCOPE
VDD
VDDO
Qx
LVCMOS
GND
-1.25V±5%
3.3V/2.5V OUTPUT LOAD TEST CIRCUIT
8304AMI
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REV. B APRIL 4, 2002
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ICS8304I
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
VDDO
2
Qx
Qy
VDDO
2
tsk(o)
OUTPUT SKEW
VDDO
PART 1
Qx
2
VDDO
2
PART 2
Qy
tsk(pp)
PART-TO-PART SKEW
70%
70%
30%
30%
Clock Inputs
and Outputs
tR
tF
INPUT AND OUTPUT RISE AND FALL TIME
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REV. B APRIL 4, 2002
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ICS8304I
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
VDD
2
CLK
VDDO
2
Q0:Q3
tPD
PROPAGATION DELAY
VDDO
VDDO
2
VDDO
2
2
Q0 :Q3
tPW
tPERIOD
tPW
odc =
tPERIOD
tPW & tPERIOD
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REV. B APRIL 4, 2002
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ICS8304I
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 5. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
128.5°C/W
115.5°C/W
112.7°C/W
103.3°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8304I is: 416
8304AMI
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REV. B APRIL 4, 2002
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ICS8304I
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - SUFFIX M
TABLE 6. PACKAGE DIMENSIONS - SUFFIX M
Millimeters
MINIMUN MAXIMUM
SYMBOL
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
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REV. B APRIL 4, 2002
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ICS8304I
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS8304AMI
Marking
8304AMI
8304AMI
Package
8 lead SOIC
Count
96 per tube -40°C to 85°C
2500 -40°C to 85°C
Temperature
ICS8304AMIT
8 lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
8304AMI
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REV. B APRIL 4, 2002
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ICS8304I
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
REVISION HISTORY SHEET
Rev
Table
3B
Page
Description of Change
Date
LVCMOS/LVTTL DC Characteristics Table, added IOH and IOL Test Conditions
to VOH and VOL rows.
B
3
4/4/02
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REV. B APRIL 4, 2002
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