83905AIL [ICSI]
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO LVCMOS/LVTTL FANOUT BUFFER; 低偏移， 1 ： 6 CRYSTAL接口到LVCMOS / LVTTL扇出缓冲器
| 型号： | 83905AIL |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1:6 CRYSTAL INTERFACE-TO LVCMOS/LVTTL FANOUT BUFFER |
| 文件： | 总16页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS83905I is a low skew, 1-to-6 LVCMOS / • 6 LVCMOS / LVTTL outputs
ICS
LVTTL Fanout Buffer and a member of the
• Outputs able to drive 12 series terminated lines
HiPerClockS™
HiPerClockS™family of High Performance Clock
Solutions from ICS. The low impedance
LVCMOS/LVTTL outputs are designed to drive
• Crystal oscillator interface
• Crystal input frequency range: 10MHz to 40MHz
• Output skew: 80ps (maximum)
50W series or parallel terminated transmission lines.The ef-
fective fanout can be increased from 6 to 12 by utilizing the
ability of the outputs to drive two series terminated lines.
• RMS phase jitter @ 25MHz, (100Hz - 1MHz):
0.26ps (typical) (VDD = VDDO = 2.5V)
The ICS83905I is characterized at full 3.3V, 2.5V, and 1.8V,
mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating
supply mode. Guaranteed output and part-to-part skew
characteristics along with the 1.8V output capabilities makes
the ICS83905I ideal for high performance, single ended appli-
cations that also require a limited output voltage.
Phase noise:
Offset
100Hz ..............-129.7 dBc/Hz
1kHz ..............-144.4 dBc/Hz
10kHz ..............-147.3 dBc/Hz
100kHz ..............-157.3 dBc/Hz
Noise Power
• 5V tolerant enable inputs
• Synchronous output enables
• Operating power supply modes:
Full 3.3V, 2.5V and 1.8V,
mixed 3.3V core/2.5V output operating supply,
mixed 3.3V core/1.8V output operating supply,
mixed 2.5V core/1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
XTAL_OUT
ENABLE 2
GND
16
15
14
13
12
11
10
9
XTAL_IN
ENABLE 1
BCLK5
VDDO
BCLK4
GND
BCLK0
BCLK1
BCLK0
VDDo
BCLK1
GND
XTAL_IN
BCLK3
VDD
BCLK2
BCLK2
BCLK3
XTAL_OUT
ICS83905I
16-LeadTSSOP
4.4mm x 5.0mm x 0.92mm body package
G Pacakge
TopView
BCLK4
BCLK5
ENABLE 1
SYNCHRONIZE
ENABLE 2
SYNCHRONIZE
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ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Output
Description
1
XTAL_OUT
Crystal oscillator interface. XTAL_OUT is the output.
Clock enable. LVCMOS / LVTTL interface levels. See Table 3.
Power supply ground.
2, 15
ENABLE 2, ENABLE 1
GND
BCLK0, BCLK1, BCLK2,
Input
3, 7, 11
4, 6, 8,
Power
Output
Clock outputs. LVCMOS / LVTTL interface levels.
10, 12, 14 BCLK3, BCLK4, BCLK5
5, 13
9
VDDO
VDD
Power
Power
Input
Output supply pin.
Core supply pin.
16
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
VDDO = 3.465V
VDDO = 2.625V
VDDO = 2V
19
18
16
pF
pF
pF
Ω
Power Dissipation Capacitance
(per output)
CPD
V
DDO = 3.3V 5%
7
7
ROUT
Output Impedance
VDDO = 2.5V 5%
VDDO = 1.8V 0.2V
Ω
10
Ω
TABLE 3. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE
Control Inputs
Outputs
BCLK0:BCLK4
ENABLE 1
ENABLE 2
BCLK5
LOW
0
0
1
1
0
1
0
1
LOW
LOW
Toggling
LOW
Toggling
Toggling
Toggling
BCLK5
BCLK0:4
ENABLE2
ENABLE1
FIGURE 1. ENABLE TIMING DIAGRAM
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ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
I
Outputs, VO
PackageThermal Impedance, θ
16 LeadTSSOP package
JA
89°C/W (0 lfpm)
-65°C to 150°C
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
10
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
ENABLE 1:2 = 00
ENABLE 1:2 = 00
mA
mA
IDDO
5
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
2.375
2.375
2.5
2.5
2.625
2.625
8
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
ENABLE 1:2 = 00
ENABLE 1:2 = 00
mA
mA
IDDO
4
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
1.6
1.6
1.8
1.8
2.0
2.0
5
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
ENABLE 1:2 = 00
ENABLE 1:2 = 00
mA
mA
IDDO
3
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
2.375
3.3
2.5
3.465
2.625
10
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
ENABLE 1:2 = 00
ENABLE 1:2 = 00
mA
mA
IDDO
4
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ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
1.6
3.3
1.8
3.465
2.0
10
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
ENABLE 1:2 = 00
ENABLE 1:2 = 00
mA
mA
IDDO
3
TABLE 4F. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 5%, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
2.375
1.6
2.5
1.8
2.625
2.0
8
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
ENABLE 1:2 = 00
ENABLE 1:2 = 00
mA
mA
IDDO
3
TABLE 4G. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD = 3.3V 5%
2
1.7
VDD + 0.3
VDD + 0.3
VDD + 0.3
0.8
V
V
V
V
V
V
V
V
V
V
V
V
V
V
ENABLE 1,
ENABLE 2
VIH
VIL
Input High Voltage
V
DD = 2.5V 5%
DD = 1.8V 0.2V
VDD = 3.3V 5%
DD = 2.5V 5%
DD = 1.8V 0.2V
DDO = 3.3V 5%; NOTE 1
DDO = 2.5V 5%; IOH = -1mA
DDO = 2.5V 5%; NOTE 1
DDO = 1.8V 0.2V; NOTE 1
V
0.65*VDD
-0.3
ENABLE 1,
ENABLE 2
Input Low Voltage
V
-0.3
0.7
V
-0.3
0.35*VDD
V
2.6
V
2
VOH
Output High Voltage
V
1.8
V
VDDO - 0.3
V
DDO = 3.3V 5%; NOTE 1
0.5
0.4
V
V
DDO = 2.5V 5%; IOL = 1mA
VOL
Output Low Voltage
V
DDO = 2.5V 5%; NOTE 1
0.45
0.35
DDO = 1.8V 0.2V; NOTE 1
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
Mode of Oscillation
Frequency
10
40
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
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ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Using External Crystal
10
DC
48
40
MHz
MHz
fMAX
Output Frequency
Using External Clock
Source; NOTE 1
100
odc
Output Duty Cycle
52
80
%
tsk(o)
Output Skew; NOTE 2, 4
RMS Phase Jitter (Random)
Output Rise/Fall Time
ps
25MHz @ (Integration
Range: 100Hz-1MHz)
tjit(Ø)
tR/tF
0.13
ps
20% to 80%
200
800
4
ps
ENABLE 1
cycles
cycles
cycles
cycles
Output Enable Time;
NOTE 3
tEN
ENABLE 2
ENABLE 1
ENABLE 2
4
4
Output Disable Time;
NOTE 3
tDIS
4
All parameters measured at IJ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Using External Crystal
10
DC
47
40
MHz
MHz
fMAX
Output Frequency
Using External Clock
Source; NOTE 1
100
odc
Output Duty Cycle
53
80
%
tsk(o)
Output Skew; NOTE 2, 5
ps
25MHz @ (Integration
Range: 100Hz-1MHz)
tjit(Ø)
tR/tF
RMS Phase Jitter (Random); NOTE 3
Output Rise/Fall Time
0.26
ps
20% to 80%
200
800
4
ps
ENABLE 1
ENABLE 2
ENABLE 1
ENABLE 2
cycles
cycles
cycles
cycles
Output Enable Time;
NOTE 4
tEN
4
4
Output Disable Time;
NOTE 4
tDIS
4
All parameters measured at IJ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Please refer to phase noise plot.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 6C. AC CHARACTERISTICS, VDD = VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Using External Crystal
10
DC
47
40
MHz
MHz
fMAX
Output Frequency
Using External Clock
Source; NOTE 1
100
odc
Output Duty Cycle
53
80
%
tsk(o)
Output Skew; NOTE 2, 4
RMS Phase Jitter (Random)
Output Rise/Fall Time
ps
25MHz @ (Integration
Range: 100Hz-1MHz)
tjit(Ø)
tR/tF
0.27
ps
20% to 80%
200
900
4
ps
ENABLE 1
cycles
cycles
cycles
cycles
Output Enable Time;
NOTE 3
tEN
ENABLE 2
ENABLE 1
ENABLE 2
4
4
Output Disable Time;
NOTE 3
tDIS
4
All parameters measured at IJ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6D. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Using External Crystal
10
DC
48
40
MHz
MHz
fMAX
Output Frequency
Using External Clock
Source; NOTE 1
100
odc
Output Duty Cycle
52
80
%
tsk(o)
Output Skew; NOTE 2, 4
RMS Phase Jitter (Random)
Output Rise/Fall Time
ps
25MHz @ (Integration
Range: 100Hz-1MHz)
tjit(Ø)
tR/tF
0.14
ps
20% to 80%
200
800
4
ps
ENABLE 1
cycles
cycles
cycles
cycles
Output Enable Time;
NOTE 3
tEN
ENABLE 2
ENABLE 1
ENABLE 2
4
4
Output Disable Time;
NOTE 3
tDIS
4
All parameters measured at IJ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 6E. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Using External Crystal
10
DC
48
40
MHz
MHz
fMAX
Output Frequency
Using External Clock
Source; NOTE 1
100
odc
Output Duty Cycle
52
80
%
tsk(o)
Output Skew; NOTE 2, 4
RMS Phase Jitter (Random)
Output Rise/Fall Time
ps
25MHz @ (Integration
Range: 100Hz-1MHz)
tjit(Ø)
tR/tF
0.18
ps
20% to 80%
200
900
4
ps
ENABLE 1
cycles
cycles
cycles
cycles
Output Enable Time;
NOTE 3
tEN
ENABLE 2
ENABLE 1
ENABLE 2
4
4
Output Disable Time;
NOTE 3
tDIS
4
All parameters measured at IJ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6F. AC CHARACTERISTICS, VDD = 2.5V 5%, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Using External Crystal
10
DC
47
40
MHz
MHz
fMAX
Output Frequency
Using External Clock
Source; NOTE 1
100
odc
Output Duty Cycle
53
80
%
tsk(o)
Output Skew; NOTE 2, 4
RMS Phase Jitter (Random)
Output Rise/Fall Time
ps
25MHz @ (Integration
Range: 100Hz-1MHz)
tjit(Ø)
tR/tF
0.19
ps
20% to 80%
200
900
4
ps
ENABLE 1
cycles
cycles
cycles
cycles
Output Enable Time;
NOTE 3
tEN
ENABLE 2
ENABLE 1
ENABLE 2
4
4
Output Disable Time;
NOTE 3
tDIS
4
All parameters measured at IJ fMAX using a crystal input unless noted otherwise.
Terminated at 50Ω to VDDO/2.
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TYPICAL PHASE NOISE AT 25MHZ (2.5V CORE/ 2.5V OUTPUT)
0
-10
25MHz
RMS Phase Jitter (Random)
-20
-30
-40
-50
-60
-70
-80
100Hz to 1MHz = 0.26ps (typical)
-90
-100
-110
-120
Raw Phase Noise Data
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 25MHZ (3.3V CORE/ 3.3V OUTPUT)
0
-10
25MHz
RMS Phase Jitter (Random)
-20
-30
-40
-50
-60
-70
-80
100Hz to 1MHz = 0.13ps (typical)
-90
-100
Raw Phase Noise Data
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
OFFSET FREQUENCY (HZ)
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ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.25V 5%
1.65V 5%
SCOPE
SCOPE
VDD
VDDO
,
VDD,
VDDO
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-1.165V 5%
-1.25V 5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.05V 5% 1.25V 5%
0.9V 0.1V
SCOPE
VDD
SCOPE
VDD
VDDO
,
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-0.9V 0.1V
-1.25V 5%
1.8V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
0.9V 0.1V
1.6V 0.025%
2.4 0.9V
0.9V 0.1V
SCOPE
SCOPE
VDD
VDD
VDDO
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-0.9V 0.1V
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
-0.9V 0.1V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
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REV. B MAY 16, 2005
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ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
VDD
2
VDDO
BCLKx
Qx
Qy
2
tPW
tPERIOD
VDDO
2
tPW
tsk(o)
x 100%
odc =
tPERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
tF
80%
20%
20%
Clock
Outputs
tR
OUTPUT RISE/FALL TIME
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ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
Figure 1A shows an example of ICS83905I crystal interface with
a parallel resonant crystal.The frequency accuracy can be fine
outs. Slightly increasing the C1 and C2 values will slightly reduce
the frequency.Slightly decreasing the C1 and C2 values will slightly
tuned by adjusting the C1 and C2 values. For a parallel crystal increase the frequency. For the oscillator circuit below, R1 can
with loading capacitance CL = 18pF, we suggest C1 = 15pF and be used, but is not required. For new designs, it is recommended
that R1 not be used.
C2 = 15pF to start with.These values may be slightly fine tuned
further to optimize the frequency accuracy for different board lay-
XTAL_I N
C1
15p
X1
18pF Parallel Crystal
0
XTAL_OU T
C2
R1 (optional)
15p
FIGURE 1. CRYSTAL OSCILLATOR INTERFACE
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ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
LAYOUT GUIDELINE
Figure 2 shows an example of ICS83905I application schematic. accurate, but minor adjustments might be required. For the
In this example, the device is operated at VDD = 3.3V and VDDO
=
LVCMOS output drivers, two termination examples are shown
in the schematic. For additional termination, examples are shown
in the LVCMOS Termination Application Note.
3.3V.The decoupling capacitors should be located as close as
possible to the power pins.The input is driven by an 18pF load
resonant quartz crystal.The tuning capacitors (C1, C2) are fairly
VDDO = 3.3V
R2
VDD = 3.3V
31
Zo = 50 Ohm
CL = 18 pf
C2
C1
15pf
15pF
LVCMOS
U1
1
16
15
14
13
12
11
10
9
XTAL_OU T
ENABLE 2
GND
BCLK0
VDDO
BCLK1
GND
BCLK2
XTAL_IN
ENABLE 2
ENABLE 1
2
3
4
5
6
7
8
ENABLE 1
BCLK5
VDDO
BCLK4
GND
BCLK3
VDD
VDD
VDDO
R3
100
Zo = 50 Ohm
R4
ICS83905I
100
LVCMOS
VDD
VDDO
Optional Termination
C3
10uF
C4
.1uF
C5
.1uF
C6
.1uF
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
FIGURE 2. Schematic of Recommended Layout
83905AGI
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REV. B MAY 16, 2005
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ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83905I is: 339
Pin compatible to MPC905
83905AGI
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REV. B MAY 16, 2005
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ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS FOR TSSOP
Millimeters
SYMBOL
Minimum Maximum
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
83905AGI
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REV. B MAY 16, 2005
14
ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS83905AGI
Marking
TBD
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
16 Lead TSSOP
ICS83905AGIT
ICS83905AGILF
ICS83905AGILFT
TBD
16 Lead TSSOP
2500 tape & reel
tube
83905AIL
83905AIL
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an“LF”suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
83905AGI
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REV. B MAY 16, 2005
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ICS83905I
LOW SKEW, 1:6 CRYSTAL INTERFACE-TO-
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Description of Change
Added Enable Timing Diagram.
Rev
Table
Page
Date
A
2
1
3/28/05
Features Section - added RMS Phase Jitter bullet.
6A - 6F
5 - 7
AC Characteristics Tables - added RMS Phase Jitter spec.
Corrected ambient operating temperature.
B
B
4/8/05
8
11
12
Added Phase Noise Plot.
Added Crystal Input Interface in Application Section.
Added schematic layout.
5/16/05
83905AGI
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REV. B MAY 16, 2005
16
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