AV9172-01CN16 [ICSI]
Low Skew Output Buffer; 低偏移的输出缓冲器
| 型号： | AV9172-01CN16 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Low Skew Output Buffer |
| 文件： | 总8页 (文件大小：401K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
AV9172
Low Skew Output Buffer
General Description
Features
The AV9172 is designed to generate low skew clocks for
clock distribution in high-performance PCs and workstations.
It uses phase-locked loop technology to align the phase and
frequency of the output clocks with an input reference clock.
Because the input to output skew is guaranteed to±500ps, the
part acts as a “zero delay” buffer.
•
AV9172-07 input is 66 MHz with 66 and 33 MHz
output buffers
•
•
•
•
AV9172-01 is pin compatible with Gazelle GA1210E
±250ps skew (max) between outputs
±500ps skew (max) between input and outputs
Input frequency range from 10 MHz to 50 MHz
(-01, -03) and from 20 MHz to 100 MHz (-07)
Output frequency range from 10 MHz to 100 MHz
(-01, -03, -07)
The AV9172 has six configurable outputs. The AV9172-01
version has one output that runs at the same phase and
frequency as the reference clock. A second output runs at the
same frequency as the reference, but can either be in phase or
180° out of phase from the input clock. Two outputs are
provided that are at twice the reference frequency and in
phase with the reference clock. The final outputs can be
programmed to be replicas of the 2x clocks or non-overlapping
two phase clocks at twice the reference frequency. The
AV9172-01 and AV9172-03 operates with input clocks
from 10 MHz to 50 MHz while producing outputs from
10 MHz to 100 MHz. The AV9172-07 operates with input
clocks from 20 to 100 MHz.
•
•
•
•
•
•
•
Special mode for two-phase clock generation
Inputs and outputs are fully TTL-compatible
CMOS process results in low power supply current
High drive, 25mA outputs
Low cost
16-pin SOIC (150-mil) or 16-pin PDIP package
The AV9172 is fabricated using CMOS technology which
results in much lower power consumption and cost compared
with the gallium arsenide-based GA1210E. The typical
operating current for the AV9172 is 50mA versus 120mA for
the GA1210E.
The use of a phase-locked loop (PLL) allows the output
clocks to run at multiples of the input clock. This permits
routing of a lower speed clock and local generation of a
required high speed clock. Synchronization of the phase
relationship between the input clock and the output clocks is
accomplished when one output clock is connected to the
input pin FBIN. The PLL circuitry matches rising edges of the
input clock and output clocks.
ICS offers several versions of the AV9172. The different
devices are shown below:
PART
DESCRIPTION
Second source of GA1210E
Clock doubler and buffer
AV9172-01
AV9172-03
AV9172-07
Clock buffer for 66 MHz input
Block Diagram
AV9172RevB060297P
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
AV9172
Pin Configuration
Functionality Table for AV9172-01
CLKIN input frequency range 10 to 50 MHz.
EN2 INV#
Q0
1X
1X
1X
1X
Q1
1X#
1X
Q2
2X
2X
2X
2X
Q3
2X
2X
2X
2X
Q4
2X
2X
1
Q5
2X
2X
2
0
0
1
1
0
1
0
1
1X#
1X
1
2
Notes:
1. 1X designates that the output is a replica of CLKIN.
2. 2X designates that the output is twice the frequency of
CLKIN, and in phase.
3. 1X# means that the output is at the same frequency and
180°C out of phase (inverted) from CLKIN.
4. Ø1 will produce a ¼ duty cycle clock of CLKIN.
5. Ø2 will produce a ¼ duty cycle clock delayed 180° from
CLKIN.
16-Pin SOIC or 16-Pin PDIP
Pin Description for AV9172-01
PIN NUMBER
PIN NAME
GND
TYPE
-
DESCRIPTION
1
2
GROUND.
GND
INV#
EN
-
GROUND.
3
Input
Input
Input
Input
-
INV# Inverts Q1 when low. (-01 [divisor select -03, -07])
EN converts Q4 and Q5 to phase clocks when high.
FEEDBACK INPUT from output Q0.
INPUT for reference clock.
4
5
FBIN
CLKIN
VDD
VDD
GND
Q0
6
7
Power supply (+5V).
8
-
Power supply (+5V).
9
-
GROUND.
10
11
12
13
14
15
16
Output
Output
Output
Output
Output
Output
-
Q0 phase and frequency same as input (1X). Feed back to pin 5.
Q1 is a 1x clock in phase or 180° out of phase with input.
Q2 twice the frequency of Q0 (2x).
Q1
Q2
Q3
Q3 twice the frequency of Q0 (2x).
Q4
Q4 is either a 2X clock or a two-phase clock - see configuration table.
Q5 is either a 2X clock or a two-phase clock - see configuration table.
Power supply (+5V).
Q5
VDD
2
AV9172
Timing Diagrams for AV9172-01
3
AV9172
Functionality Table for AV9172-03
Pin Configuration
CLKIN Input Frequency=X, input range is 10 to 50 MHz.
EN2 INV#
Q0
2X
2X
2X
2X
Q1
2X
2X
2X
2X
Q2
2X
2X
2X
2X
Q3
2X
2X
1X
1X
Q4
2X
2X
1X
1X
Q5
2X
1X
2X
1X
0
1
0
1
0
0
1
1
Example Table for AV9172-03
16-Pin SOIC or 16-Pin PDIP
(33 MHz input, all frequencies in MHz.)
EN2 INV#
Q0
66
66
66
66
Q1
66
66
66
66
Q2
66
66
66
66
Q3
66
66
33
33
Q4
66
66
33
33
Q5
66
33
66
33
0
1
0
1
0
0
1
1
Timing Diagram for AV9172-03
Note: The phase alignment between the 1X clock outputs and
reference clocks input will be either at a 0 or 180 degrees
offset if the 2X clock is used as the feedback signal (con-
nected to the FBIN pin). Which relationship occurs is totally
random and has the potential to change any time the device has
its VDD supply cycled off or the devices input clock
removed.
4
AV9172
Pin Configuration
Functionality Table for AV9172-07
CLKIN Input Frequency=X, input range is 20 to 100 MHz.
EN2 INV#
Q0
1X
1X
1X
1X
Q1
1X
1X
1X
1X
Q2
1X
1X
1X
1X
Q3
1X
1X
Q4
1X
1X
Q5
1X
0
1
0
1
0
0
1
1
0.5X
1X
0.5X 0.5X
0.5X 0.5X 0.5X
ExampleTable for AV9172-07
(66 MHz input, all frequencies in MHz.)
16-Pin SOIC or 16-Pin PDIP
EN2 INV#
Q0
66
66
66
66
Q1
66
66
66
66
Q2
66
66
66
66
Q3
66
66
33
33
Q4
66
66
33
33
Q5
66
33
66
33
0
1
0
1
0
0
1
1
Timing Diagram for AV9172-07
Absolute Maximum Ratings
VDD referenced to GND . . . . . . . . . . . . . . . . . . . . . . 7V
Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to +70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
5
AV9172
Electrical Characteristics
VDD =+5V±5%, TA=0°C to 70°C unless otherwise stated
DC Characteristics
TEST CONDITIONS
VDD=5V
PARAMETER
Input Low Voltage
SYMBOL
MIN
-
TYP
MAX
UNITS
V
VIL
VIH
IIL
-
-
0.8
-
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Supply Current
VDD=5V
2.0
-5
-5
-
V
VIN=0V
-
5
µA
µA
V
IIH
VIN=V
-
5
VOL
*
IOL=25mA
0.5
-
0.8
-
VOH*
IOH=-25mA
2.4
-
V
IDD
Unloaded, 50 MHz outputs
AC Characteristics
35
60
mA
Input Clock Rise Time
Input Clock Fall Time
Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% VDD
Output Fall time, 2.0 to 0.8V
Fall time, 80% to 20% VDD
Output Duty cycle
ICLKr*
ICLKf*
tr*
-
-
-
-
10
10
1
ns
ns
15pF load
15pF load
15pF load
15pF load
15pF load
-
0.7
ns
tr*
-
1.2
2
ns
tf*
-
0.7
1
ns
tf*
-
1.2
2
ns
dt*
45
49/51
60
55
%
Jitter, 1 sigma
T1s*
ps
Jitter, absolute
Tabs*
ae200
ps
Input Frequency (-01,-03)
Input Frequency (-07)
fi*
10
20
50
MHz
MHz
fi*
100
Output Frequency
(-01,-03, -07)
fo*
tskew1
Note 1
10
100
500
1000
250
500
MHz
ps
Note 2, 4. Input rise time
< 3ns
FBIN to IN skew
FBIN to IN skew
*
-500
1000
-250
-300
-500
±50
Note 2, 4. Input rise time
< 10ns
tskew1
*
ps
Skew between any 2 outputs at
same frequency
tskew2
*
Note 2, 4
Note 2, 4
ps
Skew between any 2 outputs at
different frequencies
ps
*Parameter guaranteed by design and characterization. Not 100% tested in production.
Notes:
1. Output frequency includes both the Fast Clock (2X or 1X) and the Slow Clock (1X or 0.5X) extremes.
2. All skew specifications are measured with a 50W transmission line, load terminated with 50W to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
6
AV9172
Typical Performance Characteristics
7
AV9172
16-Pin PDIP Package
16-Pin SOIC Package
Ordering Information
Part Number
Part Marking
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
Package Type
16 Lead CERDIP
16 Lead Plastic DIP (300 mil)
16 Lead SOIC (300 mil)
16 Lead SOIC (150 mil)
AV9172-xxCC16
AV9172-xxCN16
AV9172-xxCW16
AV9172-xxCS16
AV9172-XX
AV9172-XX
AV9172-XX
AV9172-XX
Example:
ICS XXXX-PPP M X#W
Lead Count & Package Width
Lead Count=1, 2 or 3 digits
W=.3” SOIC or .6” DIP; None=Standard Width
Package Type
C=CERDIP
N=DIP(Plastic#)
S=SOIC(150mil)
W=SOIC(300mil)
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
8
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