IC62C1024-70T [ICSI]
128K X 8 HIGH SPEED CMOS STATIC RAM; 128K ×8高速CMOS静态RAM
| 型号： | IC62C1024-70T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 128K X 8 HIGH SPEED CMOS STATIC RAM |
| 文件： | 总8页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IC62C1024
128K x 8 HIGH-SPEED CMOS STATIC RAM
ꢀEATURES
DESCRIPTION
The ICSI IC62C1024 is a low power,131,072-word by 8-bit
CMOS static RAM. It is fabricated using ICSI's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields higher
performance and low power consumption devices.
High-speed access time: 35, 45, 55, 70 ns
Low active power: 450 mW (typical)
Low standby power: 500 µW (typical) CMOS
standby
Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
ꢀully static operation: no clock or refresh
required
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
TTL compatible inputs and outputs
Single 5V (±10%) power supply
The IC62C1024 is available in 32-pin 600mil DIP, 450mil SOP
and 8*20mm TSOP-1 packages.
ꢀUNCTIONAL BLOCK DIAGRAM
512 x 2048
MEMORY ARRAY
A0-A16
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE1
CE2
CONTROL
CIRCUIT
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
ALSR005-0A
1
IC62C1024
PIN CONꢀIGURATION
32-Pin SOP and DIP
PIN CONꢀIGURATION
32-Pin 8x20mm TSOP-1
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A11
A9
A8
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
2
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
3
3
4
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
4
5
5
A6
6
6
A5
7
A9
7
A4
8
A11
OE
8
A3
9
9
A2
10
11
12
13
14
15
16
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
10
11
12
13
14
15
16
A1
A0
I/O0
I/O1
I/O2
GND
A6
A5
A4
A1
A2
A3
PIN DESCRIPTIONS
A0-A16
CE1
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
CE2
OE
WE
I/O0-I/O7
Vcc
Power
GND
Ground
OPERATING RANGE
Range
Ambient Temperature
VCC
Commercial
0°C to +70°C
5V ± 10%
5V ± 10%
Industrial
40°C to +85°C
TRUTH TABLE
Mode
WE CE1 CE2 OE
I/O Operation
Vcc Current
Not Selected
(Power-down)
X
X
H
X
X
L
X
X
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
Output Disabled
Read
H
H
L
L
L
L
H
H
H
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
Write
X
2
Integrated Circuit Solution Inc.
ALSR005-0A
IC62C1024
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
0.5 to +7.0
10 to +85
65 to +150
1.5
Unit
V
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
°C
°C
W
Power Dissipation
IOUT
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
ConditionsMax.
VIN = 0V
Unit
6
Input Capacitance
Output Capacitance
pF
pF
COUT
VOUT = 0V
8
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = 1.0 mA
VCC = Min., IOL = 2.1 mA
2.4
0.4
V
V
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
2.2
0.3
VCC + 0.5
0.8
V
V
GND ≤ VIN ≤ VCC
Com.
Ind.
5
10
5
10
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC
Com.
Ind.
5
10
5
10
µA
Notes:
1. VIL = 3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-35
ns-45
Min. Max.
ns-55
Min. Max.
ns-70
ns
Symbol Parameter
Test Conditions
CC = Max., CE = VIL
OUT = 0 mA, f = fMAX
Min. Max.
Min. Max.
Unit
I
CC
Vcc Dynamic Operating
Supply Current
V
I
Com.
Ind.
150
160
135
145
120
130
90
100
mA
I
SB
1
TTL Standby Current
(TTL Inputs)
V
CC = Max.,
Com.
Ind.
40
60
40
60
40
60
40
60
mA
mA
VIN = VIH or VIL, CE1
≥
VIH,
or CE2
≤ VIL, f = 0
I
SB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
Com.
Ind.
30
40
30
40
30
40
30
40
CE1
≥
≤
≤
VCC 0.2V,
CE2
0.2V, VIN > VCC 0.2V,
0.2V, f = 0
or VIN
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution Inc.
ALSR005-0A
3
IC62C1024
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-35
-45
Min.
-55
-70
Symbol Parameter
Min.
35
3
Max.
Max.
Min.
55
3
Max.
Min.
70
3
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
RC
Read Cycle Time
Address Access Time
Output Hold Time
CE1 Access Time
CE2 Access Time
OE Access Time
45
3
AA
35
45
55
70
OHA
ACE
1
0
35
35
10
0
45
45
20
0
55
55
25
0
70
70
35
ACE
2
DOE
(2)
(2)
LZOE
OE to Low-Z Output
OE to High-Z Output
HZOE
0
10
0
15
0
20
0
25
LZCE1(2) CE1 to Low-Z Output
3
5
7
10
10
0
LZCE2(2) CE2 to Low-Z Output
3
5
7
(2)
HZCE
CE1 or CE2 to High-Z Output
0
10
0
15
0
20
25
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in 6igure 1a.
2. Tested with the load in 6igure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1a and 1b
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
255 Ω
255 Ω
100 pF
Including
jig and
5 pF
Including
jig and
scope
scope
)igure 1a.
)igure 1b.
4
Integrated Circuit Solution Inc.
ALSR005-0A
IC62C1024
AC WAVEꢀORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
OE
tAA
tOHA
tHZOE
tDOE
tLZOE
tACE
CE
tHZCE
tLZCE
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
Integrated Circuit Solution Inc.
ALSR005-0A
5
IC62C1024
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low
Power)
-35
-45
-55
-70
Symbol Parameter
Min.
35
25
25
25
0
Max.
Min.
45
35
35
35
0
Max.
Min.
55
50
50
45
0
Max.
Min.
70
60
60
60
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
WC
SCE
SCE
AW
HA
Write Cycle Time
1
2
CE1 to Write End
CE2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
SA
0
0
0
0
(4)
PWE
WE Pulse Width
25
20
0
35
25
0
40
25
0
50
30
0
SD
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
HD
(2)
HZWE
3
10
5
15
5
20
5
25
(2)
LZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in 6igure 1a.
2. Tested with the load in 6igure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEꢀORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
t
PWE1
PWE2
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
6
Integrated Circuit Solution Inc.
ALSR005-0A
IC62C1024
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
Integrated Circuit Solution Inc.
ALSR005-0A
7
IC62C1024
ORDERING INꢀORMATION
Industrial Range: 40°C to +85°C
ORDERING INꢀORMATION
Commercial Range: 0°C to +70°C
Speed (nsꢀ Order Part No.
Package
Speed (nsꢀ Order Part No.
Package
35
35
35
IC62C1024-35WI
IC62C1024-35QI
IC62C1024-35TI
600mil DIP
35
35
35
IC62C1024-35W
IC62C1024-35Q
IC62C1024-35T
600mil DIP
450mil SOP
450mil SOP
8*20mm TSOP-1
8*20mm TSOP-1
45
45
45
IC62C1024-45W
IC62C1024-45Q
IC62C1024-45T
600mil DIP
45
45
45
IC62C1024-45WI
IC62C1024-45QI
IC62C1024-45TI
600mil DIP
450mil SOP
450mil SOP
8*20mm TSOP-1
8*20mm TSOP-1
55
55
55
IC62C1024-55WI
IC62C1024-55QI
IC62C1024-55TI
600mil DIP
55
55
55
IC62C1024-55W
IC62C1024-55Q
IC62C1024-55T
600mil DIP
450mil SOP
450mil SOP
8*20mm TSOP-1
8*20mm TSOP-1
70
70
70
IC62C1024-70W
IC62C1024-70Q
IC62C1024-70T
6600mil DIP
70
70
70
IC62C1024-70WI
IC62C1024-70QI
IC62C1024-70TI
600mil DIP
450mil SOP
450mil SOP
8*20mm TSOP-1
8*20mm TSOP-1
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
"ax: 886-3-5783000
BRANCH O""ICE:
7", NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
"AX: 886-2-26962252
http://www.icsi.com.tw
8
Integrated Circuit Solution Inc.
ALSR005-0A
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