IC62VV25616L-55TI [ICSI]
256Kx16 bit 1.8V and Ultra Low Power CMOS Static RAM; 256Kx16位1.8V和超低功耗CMOS静态RAM
| 型号： | IC62VV25616L-55TI |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 256Kx16 bit 1.8V and Ultra Low Power CMOS Static RAM |
| 文件： | 总11页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IC62VV25616L
IC62VV25616LL
Document Title
256Kx16 bit 1.8V and Ultra Low Power CMOS Static RAM
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
November 13,2001
Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
LPSR019-0A 11/13/2001
1
IC62VV25616L
IC62VV25616LL
256K x 16 1.8V ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
DESCRIPTION
The ICSI IC62VV25616L and IC62VV25616LL are low-power,
4.194,304 bit static RAMs organized as 262,144 words by 16
bits. They are fabricated using ICSI's high-performance CMOS
technology. This highly reliable process coupled with innova-
tive circuit design techniques, yields high-performance and
low power consumption devices.
• High-speed access times: 55, 70, 100 ns
• CMOS low power operation
ICC1=10mA (typical)* operating
ISB2=1µA (typical)* CMOS standby
* Typical values are measured at VCC=1.8V,
TA=25°C
When CE is HIGH (deselected) or both LB and UB are HIGH,
the device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
• TTL compatible interface levels
• Single 1.65V-2.2V Vcc power supply
• Fully static operation: no clock or refresh
required
Easy memory expansion is provided by using Chip Enable
Output and Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
The IC62VV25616L and IC62VV25616LL are packaged in the
JEDEC standare 44-pin TSOP-2 and 48-pin 6*8mm TF-BGA.
• Available in the 44-pin TSOP-2 and 48-pin
6*8mm TF-BGA
FUNCTIONAL BLOCK DIAGRAM
256K x 16
MEMORY ARRAY
A0-A17
DECODER
VCC
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2001, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
LPSR019-0A 11/13/2001
IC62VV25616L
IC62VV25616LL
PIN CONFIGURATIONS
48-Pin TF-BGA (TOP View)
44-Pin TSOP-2
A4
A3
A2
A1
A0
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
2
1
2
3
4
5
6
3
4
A0
A3
A1
A4
A2
5
LB
I/O
OE
UB
N/C
A
B
C
D
E
F
CE
6
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
7
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A17
CE
I/O
0
8
8
9
I/O
I/O
A5
A6
I/O
I/O
2
9
10
11
12
1
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
Vcc I/O
A17
NC
A14
A12
A7
I/O
I/O
I/O
I/O
Vcc
3
4
5
GND
A16
A15
A13
A10
I/O
I/O
I/O
I/O
6
14
13
NC
A8
WE
I/O
7
15
G
H
NC
A9
A11
NC
PIN DESCRIPTIONS
A0-A17
I/O0-I/O15
CE
Address Inputs
LB
Lower-byte Control (l/O0-I/O7)
Upper-byte Control (l/O8-I/O15)
No Connection
Data Input/Output
Chip Enable Input
Output Enable Input
Write Enable Input
UB
NC
OE
Vcc
GND
Power
WE
Ground
TRUTH TABLE
I/O PIN
I/O8-I/O15
Mode
WE
CE
OE
LB
UB
I/O0/-I/O7
Power
Not Selected
X
X
H
L
X
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
Stand by
Stand by
Output Disabled H
X
L
L
L
L
L
L
L
L
H
X
L
X
H
L
X
H
H
L
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
Active
Stand by
Active
Read
H
H
H
L
L
H
L
L
L
Write
X
X
X
L
H
L
Active
L
H
L
High-Z
DIN
L
L
DIN
Integrated Circuit Solution Inc.
LPSR019-0A 11/13/2001
3
IC62VV25616L
IC62VV25616LL
OPERATING RANGE
Range
Commercial
Ambient Temperature
VCC
1.65V- 2.2V
0°C to +70°C
Industrial
–40°C to +85°C
1.65V - 2.2V
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
VTERM
TBIAS
VCC
Terminal Voltage with Respect to GND
Temperature Under Bias
Vcc related to GND
–0.5 to Vcc + 0.4
–40 to +85
–0.3 to +4.0
–65 to +150
1.0
°C
V
TSTG
PT
StorageTemperature
°C
W
Power Dissipation
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = –0.1 mA
1.4
—
V
VOL
Output LOW Voltage
IOL = 0.1 mA
—
0.2
V
(1)
VIH
Input HIGH Voltage
Input LOW Voltage
Input Leakage
1.4
–0.2
–1
VCC + 0.2
V
V
(2)
VIL
ILI
0.4
1
GND ≤ VIN ≤ VCC
GND ≤ VOUT ≤ VCC, OUTPUTS DISABLED
µA
µA
ILO
Output Leakage
–1
1
Notes:
1. VIH(max.) = VCC+2.0V for pulse width less than 10 ns.
2. VIL(min.) = –2.0V for pulse width less than 10 ns.
CAPACITANCE(1)
Symbol
CIN
Parameter
Input Capacitance
Conditions
VIN = 0V
Max.
6
Unit
pF
COUT
Output Capacitance
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Circuit Solution Inc.
LPSR019-0A 11/13/2001
IC62VV25616L
IC62VV25616LL
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0.4V to 1.4V
5 ns
Input Reference Level
Output Reference Level
0.9V
0.9V
Output Load
See Figures 1
AC TEST LOADS
1 TTL
1 TTL
OUTPUT
OUTPUT
100 pF or 30PF (for 55ns)
5 pF
Including
jig and
Including
jig and
scope
scope
Figure 1
Figure 2
IC62VV25616L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-55
-70
-100
Symbol Parameter
TestConditions
Min. Max.
Min. Max.
Min. Max.
Unit
ICC1
ICC2
ISB2
Vcc Dynamic Operating
Supply Current
VCC = 1.8V,
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
20
20
—
—
15
15
—
—
10
10
mA
Vcc Dynamic Operating
Supply Current
VCC =1.8V,
IOUT = 0 mA, f = 1MHZ
Com.
Ind.
—
—
2
2
—
—
2
2
—
—
2
2
mA
µA
CMOS Standby
Current (CMOS Inputs)
VCC = Max., Other inputs= 0 - VCC
Com.
Ind.
—
—
35
50
—
—
35
50
—
—
35
50
1) CE
≥
VCC – 0.2V (CE controlled)
2) LB/ UB
≥
VCC – 0.2V (LB/ UB controlled)
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution Inc.
LPSR019-0A 11/13/2001
5
IC62VV25616L
IC62VV25616LL
IC62VV25616LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-55
-70
-100
(2)
(2)
(2)
Symbol Parameter
TestConditions
VCC = 1.8V, CE
IOUT = 0 mA, f = fMAX
VIL
Typ . Max.
Typ . Max.
Typ . Max.
7
7
Unit
mA
ICC1
ICC2
ISB2
Vcc Dynamic Operating
Supply Current
≤
VIL
Com.
Ind.
—
—
20
20
10
10
15
15
10
10
Vcc Dynamic Operating
Supply Current
VCC = 1.8V, CE
≤
Com.
Ind.
—
—
2
2
—
—
2
2
—
—
2
2
mA
µA
IOUT = 0 mA, f = 1MHZ
CMOS Standby
VCC = Max., Other inputs= 0 - VCC
Com.
Ind.
2
—
10
15
2
10
15
2
10
15
Current (CMOS Inputs)
1) CE
≥
VCC – 0.2V (CE controlled)
—
—
2) LB/ UB
≥
VCC – 0.2V (LB/ UB controlled)
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vcc=1.8V, Ta=25°C, and are not guaranteed or tested.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-55
-70
-100
Min.
Symbol Parameter
Min.
55
—
10
—
—
—
5
Max.
—
Min.
70
—
10
—
—
—
5
Max.
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
100
—
15
—
—
—
5
tAA
Address Access Time
Output Hold Time
55
—
70
—
100
—
tOHA
tACE
tDOE
CE Access Time
55
30
20
—
70
35
25
—
100
50
OE Access Time
(2)
tHZOE
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB o High-Z Output
LB. UB to Low-Z Output
30
(2)
tLZOE
—
(2)
tHZCE
0
20
—
0
25
—
0
30
(2)
tLZCE
tBA
10
—
0
10
—
0
10
—
0
—
55
25
—
70
25
—
100
35
tHZB
tLZB
0
0
0
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 1.4V and output
loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
6
Integrated Circuit Solution Inc.
LPSR019-0A 11/13/2001
IC62VV25616L
IC62VV25616LL
AC TEST LOADS
READ CYCLE NO.1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (OE Controlled)
t
RC
ADDRESS
t
AA
t
OHA
OE
CE
t
HZOE
t
DOE
LZOE
ACE
t
t
t
HZCE
t
LZCE
LB, UB
t
BA
t
HZB
t
LZB
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Circuit Solution Inc.
LPSR019-0A 11/13/2001
7
IC62VV25616L
IC62VV25616LL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-55
-70
-100
Max
Symbol
tWC
Parameter
Write Cycle Time
Min.
55
50
50
0
Max.
—
Min.
70
65
65
0
Max.
—
Min.
100
80
80
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
—
—
—
40
—
tSCE
tAW
CE to Write End
—
—
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
—
—
tHA
—
—
tSA
0
—
0
—
0
tPWB
tPWE
tSD
LB, UB Valid to End of Write
WE Pulse Width
45
45
25
0
—
60
55
30
0
—
80
80
40
0
—
—
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
—
—
tHD
—
—
(3)
tHZWE
—
5
30
—
—
5
30
—
—
5
(3)
tLZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 1.4V and output loading specified in
Figure 1.
2. The internal write time is defined by the overlap of CE LOW, and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled)
t
WC
VALID ADDRESS
SCS
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
PWE
WE
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
8
Integrated Circuit Solution Inc.
LPSR019-0A 11/13/2001
IC62VV25616L
IC62VV25616LL
WRITE CYCLE NO. 2 (WE Controlled)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE
WE
t
SA
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
WRITE CYCLE NO. 3 (UB / LB Controlled)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
t
SA
CE
LOW
t
HA
SA
t
HA
t
WE
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
Integrated Circuit Solution Inc.
LPSR019-0A 11/13/2001
9
IC62VV25616L
IC62VV25616LL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Vcc for Data Retention
TestCondition
See Data Retention Waveform
Min.
1.0
Max.
2.2
Unit
V
IDR
Data Retention Current
Vcc = 1.2V, CE
≥
Vcc – 0.2V
Com. (-L)
Com. (-LL)
—
—
15
6
µA
Ind. (-L)
—
—
20
8
Ind. (-LL)
tSDR
tRDR
Data Retention Setup Time
RecoveryTime
See Data Retention Waveform
See Data Retention Waveform
0
5
—
—
ns
ns
DATA RETENTION WAVEFORM (CE or LB/UB Controlled)
t
SDR
Data Retention Mode
tRDR
V
V
CC
DR
1.65V
1.4V
CE ≥ VCC - 0.2V
CE, LB/UB
GND
10
Integrated Circuit Solution Inc.
LPSR019-0A 11/13/2001
IC62VV25616L
IC62VV25616LL
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
55
IC62VV25616L-55TI
IC62VV25616L-55BI
TSOP-2
6*8mmTF-BGA
55
IC62VV25616L-55T
IC62VV25616L-55B
TSOP-2
6*8mmTF-BGA
70
IC62VV25616L-70TI
IC62VV25616L-70BI
TSOP-2
6*8mmTF-BGA
70
IC62VV25616L-70T
IC62VV25616L-70B
TSOP-2
6*8mmTF-BGA
100
IC62VV25616L-100TI
IC62VV25616L-100BI
TSOP-2
6*8mmTF-BGA
100
IC62VV25616L-100T
IC62VV25616L-100B
TSOP-2
6*8mmTF-BGA
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: -40°C to +85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
55
IC62VV25616LL-55TI
IC62VV25616LL-55BI
TSOP-2
6*8mmTF-BGA
55
IC62VV25616LL-55T
IC62VV25616LL-55B
TSOP-2
6*8mmTF-BGA
70
IC62VV25616LL-70TI
IC62VV25616LL-70BI
TSOP-2
6*8mmTF-BGA
70
IC62VV25616LL-70T
IC62VV25616LL-70B
TSOP-2
6*8mmTF-BGA
100
IC62VV25616LL-100TI
IC62VV25616LL-100BI
TSOP-2
6*8mmTF-BGA
100
IC62VV25616LL-100T
IC62VV25616LL-100B
TSOP-2
6*8mmTF-BGA
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
Integrated Circuit Solution Inc.
LPSR019-0A 11/13/2001
11
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