ICS1493K-17LF [ICSI]
Clock Synthesizer for Portable Systems; 时钟合成器的便携式系统
| 型号： | ICS1493K-17LF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Clock Synthesizer for Portable Systems |
| 文件： | 总11页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P R E L I M I N A R Y I N F O R M A T I O N
ICS1493-17
Clock Synthesizer for Portable Systems
Description
Features
The ICS1493-17 is a low-power, low-jitter clock
synthesizer designed to replace multiple crystals and
• Extremely low operating current (11 mA)
• Packaged in 20-pin QFN (Pb-free)
oscillators in portable audio/video systems. The device
generates a 37 MHz processor clock, a 48 MHz USB
clock, a fixed 22.5792 MHz audio clock, a selectable
24.576 MHz or 22.5792 MHz audio clock, and a 27MHz
reference clock for video. Using ICS’ proprietary mix of
analog and digital Phase-Locked Loop (PLL)
technology, the device spreads the frequency spectrum
of the 37 MHz output, reducing the peak amplitude of
by up to 16 dB. An output enable (OE) pin lowers the
chip power consumption while tri-stating all outputs.
• Input crystal or clock frequency of 27 MHz
• Output reference frequency of 27 MHz
• Fixed output frequencies of 37 MHz, 48 MHz and
22.5792 MHz
• Selectable output frequency of either 22.5792 MHz
or 24.576 MHz
• Configurable spread spectrum on 37 MHz output
• Operating core voltage of 1.8 V
• Output voltage of 1.8 V or 2.5 V
• Advanced, low-power CMOS process
Block Diagram
VDD
VDDO
2
OE
3
PLL1
(Spread)
37M
IIC
SCK
Control
Logic
SDATA
PLL2
PLL3
PLL4
48M
22/24M
22M
27M
X1
X2
Crystal
Oscillator/
Clock
27 MHz
clock or
crystal input
Buffer
5
Optional tuning
capacitors
GND
MDS 1493-17 A
1
Revision 101005
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P R E L I M I N A R Y I N F O R M A T I O N
ICS1493-17
Clock Synthesizer for Portable Systems
Pin Assignment
Output Enable Table
Clock Output State
OE
0
Normal Operation
Hi-Z
16
1
GND
48M
GND
1
VDD
Note: OE pin has an internal pull-down resistor.
VDDO
OE
37M
VDDO
22/24M
11
VDD
6
20-pin QFN
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
2
3
GND
Power Connect to ground.
48M
Output 48 MHz clock output. High impedance state when OE=1.
VDDO
Power Output voltage level. Connect to +1.8 or 2.5 V. Same voltage as pin
12.
4
5
6
OE
VDD
22M
Input
Output Enable pin. See table above. Internal pull-down resistor.
Power Connect to +1.8 V.
Output 22.5792 MHz clock output. Internal pull-down. High impedance state
when OE=1.
7
8
GND
SCK
Power Connect to ground.
2
Input
Input
I C bus clock pin. Internal pull-up resistor.
2
9
SDATA
GND
I C bus data pin. Internal pull-up resistor.
10
11
Power Connect to ground.
22/24M
Output Selectable output clock of either 22.5792M or 24.576M. See table.
Internal pull-down. High impedance state. OE=1.
12
13
VDDO
37M
Power Output voltage level. Connect to +1.8 or 2.5 V. Same voltage as pin 3.
Output Spread spectrum 37 MHz clock output. See table. Internal pull-down.
High impedance state when OE=1.
14
15
16
17
VDD
GND
GND
27M
Power Connect to +1.8 V.
Power Connect to ground.
Power Connect to ground.
Output 27 MHz reference clock output. Internal pull-down. High impedance
state when OE=1.
MDS 1493-17 A
2
Revision 101005
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P R E L I M I N A R Y I N F O R M A T I O N
ICS1493-17
Clock Synthesizer for Portable Systems
Pin
Number
Pin
Name
Pin
Type
Pin Description
18
19
20
VDD
X2
Power Connect to +1.8 V.
Output Connect to 27 MHz crystal or float for clock input.
X1
Input
Crystal connection. Connect to 27 MHz crystal or clock input.
.
External Components
Decoupling Capacitor
PCB Layout Recommendations
As with any high-performance mixed-signal IC, the
ICS1493-17 must be isolated from system power
supply noise to perform optimally.
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
2
I C External Resistor Connection
3) To minimize EMI, the 33Ω series termination resistor
should be placed close to the clock output.
The SCK and SDATA pins can be connected to any
voltage between 1.71 V and 2.625 V.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS1493-17. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Crystal Load Capacitors
No external crystal load capacitors are required. To
save discrete component cost, the ICS1493-17
integrates on-chip capacitance to support a crystal with
CL=10 pF. It is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device.
MDS 1493-17 A
3
Revision 101005
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P R E L I M I N A R Y I N F O R M A T I O N
ICS1493-17
Clock Synthesizer for Portable Systems
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS1493-17. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs
-0.5 V to 5 V
-0.5 V to VDD+0.5 V
-0.5 V to 2.5V+0.5 V
-65 to +150°C
125°C
All Outputs
Storage Temperature
Junction Temperature
Soldering Temperature
ESD (HBM)
260°C
2000V min.
3
MSL (Moisture Sensitivity Level)
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+80
Units
Ambient Operating Temperature
-10
°C
V
Power Supply Voltage (measured in respect to GND)
Output Power Supply Voltage (with respect to GND)
+1.70
+1.71
+2.00
+2.625
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 1.8 V -0.1 V/+0.2 V, VDDO=2.5 V 5ꢀ% Ambient Temp -10°C to +80°C
Parameter
Operating Voltage
Supply Current
Symbol
VDD
Conditions
Min.
Typ.
Max.
2.0
16
Units
V
1.7
IDD
13
11
mA
mA
V
No load,VDDO=2.5 V
No load,VDDO=1.8 V
15
Input High Voltage
V
0.7VDD
IH
Input Low Voltage
V
0.3VDD
V
IL
Output High Voltage
Output Low Voltage
V
I
I
= -2 mA
= +2 mA
0.8VDDO
V
OH
OH
V
0.2VDDO
V
OL
OL
Input Capacitance, inputs
Load Capacitance, X1 and X2
C
5
5
pF
pF
IN
C
No internal load
capacitance
L
MDS 1493-17 A
4
Revision 101005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
P R E L I M I N A R Y I N F O R M A T I O N
ICS1493-17
Clock Synthesizer for Portable Systems
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Internal Pull-down Resistor
R
75
250
kΩ
OE, 48M, 22M,
PD
22/24M, 37M, 27M
Internal Pull-up Resistor
R
SCK, SDATA
100
500
kΩ
Pu
AC Electrical Characteristics
Unless stated otherwise, VDDO = 2.5 V 5ꢀ, Ambient Temperature -10°C to +80°C
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Input Frequency
f
27
1.5
1.5
46
MHz
ns
IN
Output Rise Time
Output Fall Time
t
20% to 80%, Note 1
80% to 20%, Note 1
VO=VDDO/2
0.7
0.7
33
2.2
2.2
68
OR
t
ns
OF
Output Impedance
Output Clock Duty Cycle
R
Ω
O
VDDO/2, 27 MHz,
Note 1
40
50
60
%
VDDO/2, Note 1
All outputs
45
30
50
0
55
%
ppm
kHz
ps
Frequency Synthesis Error
Modulation Rate
Short Term Jitter
Long Term Jitter
35
150
40
Cycle-to-Cycle
27 MHz, n=1000
48 MHz, n=1000
300
600
800
1.2
ps
Long Term Jitter
ps
Long Term Jitter
22M and 22/24M,
n=1000
ns
Long Term Jitter
Power-up Time
37 MHz non-spread,
n=1000
1.5
1.5
6
3
ns
t
ms
From minimum VDD
to outputs stable
PU
Output Enable Time
Output Disable Time
Switching Time
50
20
ns
ns
ns
100
22/24M, Note 2
Note 1: Measured with a 5 pF load.
Note 2: Finish from prior cycle to start of new cycle.
MDS 1493-17 A
5
Revision 101005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
P R E L I M I N A R Y I N F O R M A T I O N
ICS1493-17
Clock Synthesizer for Portable Systems
AC Electrical Characteristics
Unless stated otherwise, VDDO = 1.8 V 0.1 V, Ambient Temperature -10°C to +80°C
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Input Frequency
f
27
2.2
2.2
46
MHz
ns
IN
Output Rise Time
Output Fall Time
t
20% to 80%, Note 1
80% to 20%, Note 1
VO=VDDO/2
1.1
1.1
33
3.3
3.3
68
OR
t
ns
OF
Output Impedance
Output Clock Duty Cycle
R
Ω
O
VDDO/2, 27 MHz,
Note 1
40
50
60
%
VDDO/2, Note 1
Note 1
45
30
50
225
0
55
%
ps
Absolute Clock Period Jitter
Frequency Synthesis Error
Modulation Rate
All outputs
ppm
kHz
ps
35
40
375
900
750
1200
Short Term Jitter
Cycle-to-cycle
225
Long Term Jitter
27 MHz, n=1000
48 MHz, n=1000
ps
Long Term Jitter
ps
Long Term Jitter
22M and 22/24M,
n=1000
ps
Long Term Jitter
Power-up Time
37 MHz, n=1000
2.5
1.5
9
4
ns
t
ms
From minimum VDD
to outputs stable
PU
Output Enable Time
Output Disable Time
Switching Time
50
20
ns
ns
ns
250
22/24M, Note 2
Note 1: Measured with a 5 pF load.
Note 2: Finish from prior cycle to start of new cycle.
MDS 1493-17 A
6
Revision 101005
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P R E L I M I N A R Y I N F O R M A T I O N
ICS1493-17
Clock Synthesizer for Portable Systems
Serial Data Interface
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the
controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest
byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write
and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed
byte is encoded in the command code, as described in the following table.
Bit
7
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations,
these bits should be '0000000'.
The block write and block read protocol is outlined in the table below, followed by the corresponding byte write and
byte read protocol. The slave receiver address is 11010010 (D2h).
Block Write Protocol
Description
Block Read Protocol
Description
Bit
1
Bit
1
Start
Start
2:8
9
Slave address - 7 bits
Write = 0
2:8
9
Slave address - 7 bits
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command code — 8 bit
11:18
Command code - 8 bit
‘00000000’ stands for block operation
‘00000000’ stands for block operation
19
20:27
28
Acknowledge from slave
Byte count — 8 bits
Acknowledge from slave
Data byte 0 — 8 bits
Acknowledge from slave
Data byte 1 — 8 bits
Acknowledge from slave
.............................
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address — 7 bits
Read = 1
29:36
37
29
Acknowledge from slave
Byte count from slave — 8 bits
Acknowledge from master
Data byte from slave — 8 bits
Acknowledge from master
Data byte from slave — 8 bits
Acknowledge from master
Data byte N from slave — 8 bits
Not Acknowledge from master
Stop
38:45
46
30:37
38
....
39:46
47
....
Data byte (N-1) — 8 bits
Acknowledge from slave
Data byte N — 8 bits
Acknowledge from slave
Stop
....
48:55
56
....
....
....
....
....
....
MDS 1493-17 A
7
Revision 101005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
P R E L I M I N A R Y I N F O R M A T I O N
ICS1493-17
Clock Synthesizer for Portable Systems
.
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Bit
1
Description
Start
Start
2:8
9
Slave address - 7 bits
Write = 0
2:8
9
Slave address - 7 bits
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command code — 8 bit
11:18
Command code — 8 bit
‘10000000’ stands for byte operation,
bits[1:0] of the command code represents
the offset of the byte to be accessed
‘10000000’ stands for byte operation, bits[1:0]
of the command code represents the offset of
the byte to be accessed
19
20:27
28
Acknowledge from slave
Data byte from master— 8 bits
Acknowledge from slave
Stop
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address — 7 bits
Read = 1
29
29
Acknowledge from slave
Data byte from slave — 8 bits
Not Acknowledge from master
Stop
30:37
38
39
Byte 0: Vendor ID% Revision Code
Bit
7
@Pup
Name
Revision Code(MSB)
Revision Code
Revision Code
Revision Code(LSB)
Vendor ID(MSB)
Vendor ID
Description
Revision Code
Revision Code
Revision Code
Revision Code
Vendor ID
0
0
0
1
1
1
1
1
6
5
4
3
2
Vendor ID
1
Vendor ID
Vendor ID
0
Vendor ID(LSB)
Vendor ID
MDS 1493-17 A
8
Revision 101005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
P R E L I M I N A R Y I N F O R M A T I O N
ICS1493-17
Clock Synthesizer for Portable Systems
Byte 1: Control Register
Bit
@Pup
Name
Description
7
1
REF
REF Output Enable
0 = Disable, Output pulled low, 1 = Enable
6
1
37SS
37SS Output Enable
0 = Disable, Output pulled low, corresponding PLL shut off.
1 = Enable
5
4
3
1
1
0
48M
22/24M
22M
48M Output Enable
0 = Disable, Output pulled low, 1 = Enable
22/24M Clock Output Enable
0 = Disable, Output pulled low, 1 = Enable
22M Output Enable
0 = Disable, Output pulled low and corresponding PLL off,
1 = Enable
2
1
0
1
1
1
Reserved
Reserved
Reserved
Reserved
22/24M SEL
22/24M Clock Select
1 = 24.576 MHz, 0 = 22.5792 MHz
Byte 2: Control Register
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
SS Table
Reserved
Reserved
Reserved
Reserved
Reserved
6
5
4
3
2
Bit 2:0=000: No Spread
Bit 2:0=001: -0.5% Spread
Bit 2:0=010:-1.0% Spread
Bit 2:0=011: No Spread
Bit 2:0=100: -2.0% Spread
Bit 2:0=101: No Spread
Bit 2:0=110: -3.0% Spread
Bit 2:0=111: No Spread
1
0
1
0
SS Table
SS Table
MDS 1493-17 A
9
Revision 101005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
P R E L I M I N A R Y I N F O R M A T I O N
ICS1493-17
Clock Synthesizer for Portable Systems
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
Still air
39
36
34
°C/W
°C/W
°C/W
JA
JA
JA
1 m/s air flow
2.5 m/s air flow
Marking Diagram
16
1
93K17L
######
YYWW
11
6
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year and the week number that the part was assembled.
3. “L” denotes Pb (lead) free package.
4. Bottom marking: (origin). Origin = country of origin if not USA.
MDS 1493-17 A
10
Revision 101005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
P R E L I M I N A R Y I N F O R M A T I O N
ICS1493-17
Clock Synthesizer for Portable Systems
Package Outline and Package Dimensions (20-pin QFN)
Package dimensions are kept current with JEDEC Publication No. 95
(Ref)
ND & NE
Even
Seating Plane
(ND-1)x
(Ref)
e
A1
Index Area
(Typ)
If ND & NE
are Even
L
A3
e
2
N
1
2
N
Anvil
Singulation
1
2
(NE-1)x
(Ref)
e
-- or --
E2
E
E2
2
Sawn
Singulation
Top View
b
A
C
(Ref)
ND & NE
Odd
e
Thermal Base
D
D2
2
C
D2
0.08
Millimeters
Symbol
Min
0.80
0
0.20 Reference
0.18
Max
1.00
0.05
A
A1
A3
b
0.30
e
0.50 BASIC
N
20
N
N
5
5
D
E
D x E BASIC
4.00 x 4.00
D2
E2
L
1.95
1.95
0.45
2.25
2.25
0.75
Ordering Information
Part / Order Number
ICS1493K-17LF
Marking
see page 10
Shipping Packaging
Tubes
Package
20-pin QFN
20-pin QFN
Temperature
-10 to +80°C
-10 to +80°C
ICS1493K-17LFT
Tape and Reel
Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 1493-17 A
11
Revision 101005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
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