ICS1524 [ICSI]
Dual Output Phase Controlled SSTL-3/PECL Clock Generator; 双路输出相位控制SSTL - 3 / PECL时钟发生器
| 型号： | ICS1524 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Dual Output Phase Controlled SSTL-3/PECL Clock Generator |
| 文件： | 总24页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS1524
Systems, Inc.
Dual Output Phase Controlled SSTL_3/PECL Clock Generator
General Description
Features
•
Wide input frequency range
The ICS1524 is a low-cost, very high-performance
frequency generator and phase controlled clock synthe-
sizer. It is perfectly suited to phase controlled clock
synthesis and distribution as well as line-locked and
genlocked applications.
• 8 kHz to 100 MHz
•
•
•
250 MHz balanced PECL differential outputs
150 MHz single-ended SSTL_3 clock outputs
Dynamic Phase Adjust (DPA) for DPACLK
outputs
The ICS1524 offers two channels of clock phase con-
trolled outputs; CLK and DPACLK. These two output
channels have both 250 MHz PECL differential and 150
MHz SSTL_3 single-ended output pins. The CLK output
channel has a fixed phase relationship to the PLL’s input
and the DPACLK uses the Dynamic Phase Adjust cir-
cuitry to allow control of the clock phase relative to input
signal.
• Software controlled phase adjustment
• 360o Adjustment down to 1/64 clock
increments
•
•
•
External or internal loop filter selection
Uses 3.3 VDC Inputs are 5 volt tolerant.
I2C-bus serial interface runs at either low speed
(100 kHz) or high speed (400 kHz).
Optionally, the CLK outputs can operate at half the clock
rate and phase aligned with the DPACLK channel, en-
abling deMUXing of multiplexed analog-to-digital
converters. The FUNC pin provides either the regener-
ated input from the phase-locked loop (PLL) divider
chain output or a re-synchronized and sharpened input
HSYNC.
•
Hardware and Software PLL Lock detection
Applications
•
•
•
Generic Frequency Synthesis
LCD Monitors and Projectors
Genlocking Multiple Video Systems
The advanced PLL uses either its internal program-
mable feedback divider or an external divider and is
programmed by a standard I2C-bus™ serial interface.
Block Diagram
Pin Configuration
Loop
Filter
IREF
CLK+
CLK–
VDDD
VSSD
SDA
1
2
24
23
22
21
20
19
18
17
16
15
14
13
(PECL)
(PECL)
CLK
CLK+/-
3
DPACLK+ (PECL)
DPACLK– (PECL)
VSSQ
SCL
4
HSYNC
PDEN
EXTFB
HSYNC
EXTFIL
XFILRET
VDDA
VSSA
5
6
DPACLK
DPACLK+/-
FUNC
VDDQ
7
OSC
I2C
DPACLK (SSTL)
8
CLK
FUNC
(SSTL)
(SSTL)
9
10
11
12
LOCK/REF (SSTL)
2
I CADR
OSC
24 Pin 300-mil SOIC
I2C-bus is a trademark of Philips Corporation.
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
ICS1524 Rev C 01/31/2003
ICS1524
Document Revision History
Rev A
ICS1523 Rev T Datasheet used as a starting template
New Block Diagram substituted for old 1523 one
Removed reference to CLK / 2 Functionality
Created a set of clock outputs that bypass the DPA
External PDEN is now the IN-SEL MUX control bit
Text descriptions changed to support new 1524 block diagram
Rev B
Rev C
Replaced page 15 “Layout Guidelines”
Replaced SIOC Package diagram on page 22
“Advanced Status” removed
Redrew front page graphics for clairity
Corrected Chip Revision and Chip Version values on page 5
Changed Title on Page 1
Minor format changes to pages 8 and 21
Corrected pin names on page 10
ICS1524 Rev C 01/31/2003
2
LOCK/REF (14)
PDEN (5)
Osc_Div
PD_Pol
Reg 0:1
Reg 7:0-6
En_DLS
PDen
Reg 0:7 EXTFIL (8) XFILRET (9)
Reg 0:0
Lock
Osc
OSC
(12)
Logic
En_PLS
Reg 0:6
Divider
Ref_Pol
Reg 0:2
1
MUX
IREF
(24)
PECL
Bias
Phase/
Freq
HSYNC
(7)
VCO
0
Filter
Charge
Pump
Select
Detector
PSD
Fil_Sel
Post-
Scaler
Divider
Reg 1:4-5
Reg 4:7
Fbk_Sel
PLL_Lock
Reg 12:1
Fbk_Pol
Reg 0:3
Reg 0:4
Out_Scl
PFD
Reg 1:0-2
Reg 6:6-7
Int Filter
EXTFB
(6)
1 MUX
DPA_Lock
Reg 12:0
Output
Scaler
0
DPACLK (17)
OE_Tck
Reg 6:1
Feedback
Divider
DPACLK+ (21)
DPACLK– (20)
DPA_OS
+
+
Reg 4:0-5
SDA
(3)
OE-Pck
Reg 6:0
I2C
FDB1
DPA_Res
Reg 5:0-1
Reg: 3:0-3
Dynamic
FDB0
2:0-7
Interface
SCL
(4)
Reg
CLK (16)
Phase
Adjust
OE_T2
1MUX
Reg 6:3
I2CADR
(13)
CLK+ (23)
CLK– (22)
0
Func_Sel
Reg 0:5
OE_P2
Reg
6:2
Ck2_Inv
Reg 6:5
1MUX
Power-
On
FUNC (15)
0
Reset
OE_F
Reg 6:4
ICS1524 Block Diagram
June 25, 2001
ICS1524
Pin Descriptions
PIN NO.
PIN NAME
VDDD
VSSD
SDA
TYPE
DESCRIPTION
Digital supply
Digital ground
Serial data
Serial clock
PFD enable
External feedback
Horizontal sync
External filter
External filter return
Analog supply
Analog ground
Oscillator
COMMENTS
3.3V to digital sections
1
2
3
4
5
6
7
8
9
PWR
PWR
IN/OUT
IN
Ground for digital sections
I2C-bus1
SCL
I2C-bus1
PDEN
EXTFB
HSYNC
EXTFIL
XFILRET
VDDA
VSSA
OSC
IN
IN
IN
IN
Suspends charge pump1
External divider input to PFD1
Clock input to PLL1
External PLL loop filter
External PLL loop filter return
3.3V for analog circuitry
Ground for analog circuitry
Input from crystal oscillator package1, 2
IN
10
11
12
PWR
PWR
IN
Chip I2C address select
13
I2CADR
IN
I2C address
Low = 4Dh read, 4Ch write
High = 4Fh read, 4Eh write
14
15
16
17
18
19
20
21
22
23
24
LOCK/REF
FUNC
CLK
DPACLK
VDDQ
VSSQ
DPACLK–
DPACLK+
CLK–
CLK+
IREF
SSTL
SSTL
SSTL
SSTL
PWR
PWR
PECL
PECL
PECL
PECL
IN
Lock indicator/reference
Function output
Pixel clockt
DPA Delayed Clock
Output driver supply
Output driver ground
DPA Delayed PECL clock -
DPA Delayed PECL clock +
PECL clock -
Displays PLL or DPA lock or REF input
SSTL_3 selectable HSYNC output
Non-Delayed SSTL_3 Clock
DPA Delayed SSTL_3 Clock
3.3V VDD for output drivers
Ground for output drivers
DPA Delayed Inverted PECL Clock Open drain.
DPA Delayed PECL Clock
Open drain.
Non-Delayed Inverted PECL Clock Open drain.
PECL clock +
Reference current
Non-Delayed PECL Clock
Open drain.
Reference current for PECL outputs
Notes:
1. These LVTTL inputs are 5V-tolerant.
2. Connect to ground if unused.
ICS1524 Rev C 01/31/2003
4
ICS1524
I2C Register Map Summary
Register
Index
0h
Reset
Value
Name
Access
Bit Name
Bit #
Description
Input Control
R / W
PDen
PD_Pol
Ref_Pol
Fbk_Pol
Fbk_Sel
Func_Sel
EnPLS
0
1
2
3
4
5
6
7
1
0
0
0
0
0
1
0
Phase Detector Enable
Phase Detector Input Select
External Reference Polarity
External Feedback Polarity
External Feedback Select
Function Out Select
(0=Disable 1=Enable)
(0=Positive Edge, 1=Negative Edge)
(0=Positive Edge, 1=Negative Edge)
(0=Internal Feedback, 1=External)
(0=Recovered HSYNC, 1=Input HSYNC)
Enable PLL Lock/Ref Status Output
Enable DPA Lock/Ref Status Output
(0=Disable 1=Enable)
(0=Disable 1=Enable)
EnDLS
1h
Loop Control
R / W *
PFD0-2
Reserved
PSD0-1
0-2
3
4-5
6-7
0
0
0
0
Phase Detector Gain
Reserved
Post-Scaler Divider
Reserved
(0 = /2, 1 = /4, 2 = /8, 3 = /16)
Reserved
2h
3h
FdBk Div 0
FdBk Div 1
R / W *
R / W *
FBD0-7
0-7
FF
PLL FeedBack Divider LSBs (bits 0-7) *
FBD8-11
Reserved
0-3
4-7
F
0
PLL Feedback Divider MSBs (bits 8-11) *
Reserved
4h
DPA Offset
R / W
DPA_OS0-5
Reserved
Fil_Sel
0-5
6
7
0
0
1
Dynamic Phase Aligner Offset
Reserved
Loop Filter Select
(0=External, 1=Internal)
5h
6h
DPA Control
R / W ** DPA_Res0-1
Metal_Rev
0-1
2-7
3
0
DPA Resolution
Metal Mask Revision Number
(0=16 delay elements, 1=32, 2=Reserved, 3=64)
Output Enables
R / W
OE_Pck
OE_Tck
OE_P2
OE_T2
OE_F
0
1
2
3
4
1
1
1
1
1
0
0
Output Enable for PECL DPACLK
Output Enable for STTL_3 DPACLK
Output Enable for PECL CLK
Output Enable for STTL_3 CLK
Output Enable for STTL_3 FUNC
( 0=High Z, 1=Enabled)
( 0=High Z, 1=Enabled)
( 0=High Z, 1=Enabled)
( 0=High Z, 1=Enabled)
( 0=High Z, 1=Enabled)
Ck2_Inv
Out_Scl
5
6-7
Select non-delayed CLK (1) or DPA delayed CLK/2 (0) on CLKx pins
SSTL DPACLK (Pin 17) Scaler (0 = ÷1, 1 = ÷2, 2 = ÷4, 3 = ÷8)
7h
8h
Osc_Div
Reset
R / W
Write
Osc_Div 0-6
In-Sel
0-6
7
0
1
Osc Divider modulus
RESERVED
DPA
PLL
0-3
4-7
x
x
Writing xA hex resets DPA and loads working register 5
Writing 5x hex resets PLL and loads working registers 1-3
10h
11h
12h
Chip Ver
Chip Rev
Rd_Reg
Read
Read
Read
Chip Ver
Chip Rev
0-7
0-7
18
01
Chip Version 17 hex
Chip Revision C2 hex
DPA_Lock
PLL_Lock
Reserved
0
1
2-7
N/A DPA Lock Status
N/A PLL Lock Status
0
(0=Unlocked, 1=Locked)
(0=Unlocked, 1=Locked)
Reserved
* Identifies double-buffered registers. Working registers are loaded during software PLL reset.
** Identifies double-buffered register. Working registers are loaded during software DPA reset.
ICS1524 Rev C 01/31/2003
5
ICS1524
Detailed Register Description
Name: Input Control
Register: 0h
Index: Read/Write
Bit Name Bit # Reset Value Description
PDen
0
1
2
3
4
5
6
7
1
0
0
0
0
0
1
0
Phase detector Enable
PD_Pol
Ref_Pol
Fbk_Pol
Fbk_Sel
Func_Sel
EnPLS
Phase/Frequency Detector Input MUX Control
Phase/Frequency Detector External Reference Polarity
External Reference Feedback Polarity
External Feedback Select
Function Output Select
Enable PLL Lock Status Output on LOCK/REF pin
Enable DPA Lock Status Output on LOCK/REF pin
EnDLS
Bit Name
Description
PD_POL
PDen
Phase/Frequency Detector
Input Supplied with...
OSC In
0
PDen
RESERVED
Bit 1
Pin 5
0
0
1
1
0
1
0
1
HSYNC In
HSYNC In
OSC In
1
2
PD_Pol
Input MUX Control
Ref_Pol
Phase/Frequency Detector External Reference Polarity —
Edge of input signal on which Phase Detector triggers.
0 = Rising Edge (default)
1 = Falling Edge
3
Fbk_Pol
External Reference Feedback Polarity — Edge of EXTFB (pin 6) signal on which
Phase/Frequency Detector triggers when external feedback is used (Reg0 [4]=1).
0 = Positive Edge (default)
1 = Negative Edge
4
5
Fbk_Sel
External Feedback Select
0 = Internal Feedback (default)
1 = External Feedback
Func_Sel
Function Output Select — Selects re-clocked output to FUNC (pin 15).
0 = Recovered HSYNC (default). Regenerated HSYNC output.
1 = External HSYNC. Schmitt-trigger conditioned input from HSYNC (pin 7).
6
7
EnPLS
EnDLS
Enable LOCK/REF (pin14) Output
EnPLS EnDLS IN_SEL
LOCK/REF(14)
0
0
0
1
0
1
0
N/A
N/A 1 if DPA locked, 0 otherwise
N/A 1 if PLL locked, 0 otherwise
Post Schmitt trigger
1
1
1
1
0
HSYNC(7) XOR Ref_Pol
1
F
÷ Osc_Div
osc
ICS1524 Rev C 01/31/2003
6
ICS1524
Name: Loop Control Register
Register: 1h
Index: Read /Write*
Bit Name Bit # Reset Value Description
PFD0-2
Reserved
PSD0-1
Reserved
0-2
0
0
0
0
Phase Frequency Detector Gain
3
Reserved
4-5
6-7
Post-Scaler Divider
Reserved
Bit Name
Description
0-2 PFD0-2
Phase/Frequency Detector Gain
Bit 2
Bit 1
Bit 0
PFD Gain (µA/2π rad)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
16
32
64
128
3
Reserved
4-5 PSD0-1
Post-Scaler Divider — Divides the output of the VCO to the DPA and Feedback Divider.
Bit 5
Bit 4
PSD Divider
0
0
1
1
0
1
0
1
2 (default)
4
8
16
6-7 Reserved
Double-buffered register. Actual working registers are loaded during software PLL reset.
See register 8h for details.
*
ICS1524 Rev C 01/31/2003
7
ICS1524
Name: Feedback Divider 0 Register / Feedback Divider 1 Register
Register: 2h, 3h
Index: Read/Write*
Bit Name Index Bit # Reset Value Description
FBD 0-7
2
0-7
FF
PLL Feedback Divider LSBs (0-7).* When Bit 0 = 0, then the total
number of clocks per line is even. When Bit 0 = 1, then the total
number of clocks is odd.
PLL Feedback Divider MSBs (8-11)*
Reserved
FBD8-11
Reserved
3
3
0-3
4-7
F
The value that is programmed into these two registers, plus a value of 8, defines the total number of clock periods that the ICS
1524 generates between HSYNCs. Program these registers with the total number of horizontal clocks per line minus 8.
Reg 3
Reg 2
3
2
1
0
7
6
5
4
3
2
1
0
Feedback Divider Modulus
=
+8
12 ≤ Feedback Divider Modulus ≤ 4103
Double-buffered registers. Actual working registers are loaded during software PLL reset.
See Register 8h for details.
*
Name: DPA Offset Register
Register: 4h
Index: Read/Write
Bit Name
Bit # Reset Value Description
DPA_OS0-5
Reserved
Fil_Sel
0-5
0
0
0
Dynamic Phase Adjust Offset
6
Reserved
7
Loop Filter Select
Bit Name
Description
0-5
DPA_OS0-5
Dynamic Phase Adjust Offset.
Selects clock edge offset in discrete steps from zero to one clock period minus one step.
Resolution (number of delay elements per clock cycle) is selected by DPA_Res0-1 (Reg 5:0-1).
Note: Offsets equal to or greater than one clock period are neither recommended nor supported.
Example: For DPA_Res0-1=01H, the clock can be delayed from 0 to 31 steps.
7
Fil_Sel
Selects external loop filter (0) or internal loop filter (1).
The use of an external loop filter is strongly recommended for all designs. Typical loop filter
values are 6.8K Ohms for the series resistor, 3300 pF RF-type capacitor for the series capacitor,
and 33 pF for the shunt capacitor.
ICS1524 Rev C 01/31/2003
8
ICS1524
Name: DPA Control Register
Register: 5h
Index: Read /Write*
Bit Name
Bit # Reset Value Description
DPA_Res0-1
0-1
3
Dynamic Phase Adjust Resolution Select.
Metal_Rev
2-7
0
Metal Mask Revision Number.
Bit
Name
Description
0-1
DPA_Res0-1
Dynamic Phase Adjust (DPA) Resolution Select.
It is not recommended to use the DPA above 160 MHz.
CLK Range, MHz
48
Bit 1 Bit 0 Delay Elements
0
0
1
1
0
1
0
1
16
32
Reserved
64
160
24
80
12
40
2-7
Metal_Rev
Metal Mask Revision Number.
After power-up, register bits 7:2 must be written with 111111. After this write,
a read indicates the metal mask revision, as below.
Revision Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
A
B
1
0
1
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
C1
C2
D
E
F
G
Double-buffered register. Actual working registers are loaded during software DPA reset.
See register 8h for details.
*
ICS1524 Rev C 01/31/2003
9
ICS1524
Name: Output Enable Register
Register: 6h
Index: Read/Write
Bit Name Bit # Reset Value Description
OE_Pck
OE_Tck
OE_P2
OE_T2
OE_F
0
0
0
0
0
0
0
0
Output Enable for DPACLK Outputs (PECL, Pins 21, 20 )
Output Enable for DPACLK Output (SSTL_3 Pin 17)
Output Enable for CLK Outputs (PECL, Pins 23, 22)
Output Enable for CLK Output (SSTL_3, Pin 16)
Output Enable for FUNC Output (SSTL_3, Pin 15)
Select CLK Output Source (Pins 23, 22, 16)
1
2
3
4
Sel_1X
Out_Scl
5
6-7
CLK Output Scaler (SSTL_3, Pin 16)
Bit
Name
Description
0
OE_Pck
Output Enable for DPACLK Outputs (PECL)
0 = High Z
1 = Enabled
1
OE_Tck
OE_P2
OE_T2
OE_F
Output Enable for DPACLK Output (SSTL_3)
0 = High Z
1 = Enabled
2
Output Enable for CLK Outputs (PECL)
0 = High Z
1 = Enabled
3
Output Enable for CLK Output (SSTL_3)
0 = High Z
1 = Enabled
4
Output Enable for FUNC Output (SSTL_3)
0 = High Z
1 = Enabled
5
Ck2_Inv
Out_Scl
Select CLK Output Source (Pins 23, 22, 16)
0 = Half Speed DPA Delayed clock to CLK outputs
1 = Full Speed non-DPA Delayed clock to CLK outputs
6-7
Clock (CLK, pin 16) Scaler
Bit 7
Bit 6
CLK Divider
0
0
1
1
0
1
0
1
1
2
4
8
ICS1524 Rev C 01/31/2003
10
ICS1524
Name: Oscillator Divider Register
Register: 7h
Index: Read /Write
Bit Name
Bit # Reset Value Description
Osc_Div 0-6
0-6
0
Osc Divider Modulus
In_Sel
7
1
Input Select
Bit
Name
Description
0-6
Osc_Div 0-6
Oscillator Divider Modulus.
Divides the input from OSC (pin 12) by the set modulus.
The modulus equals the programmed value, plus 2.
Therefore, the modulus range is from 3 to 129.
7
In_Sel
Input Select — Selects the input to the Phase/Frequency Detector
0 = HSYNC
1 = Osc Divider
Name: RESET Register
Register: 8h
Index: Write
Bit Name
Bit # Reset Value Description
DPA Reset
0-3
x
Writing xAh to this register resets DPA working register 5
PLL Reset
4-7
x
Writing 5xh to this register resets PLL working registers 1-3
Bit
Name
Description
0 -3
4-7
DPA
PLL
Writing xAh to this register resets DPA working register 5
Writing 5xh to this register resets PLL working registers 1-3
Value
xA
Resets
DPA
5x
PLL
5A
DPA and PLL
ICS1524 Rev C 01/31/2003
11
ICS1524
Name: Chip Version Register
Register: 10h
Index: Read
Bit Name
Bit # Reset Value Description
Chip Ver
0-7
17
Chip Version 24 (18h)
Name: Chip Revision Register
Register: 11h
Index: Read
Bit Name
Bit # Reset Value Description
Chip Rev
0 -7
01+
Initial value 01h.
+Value increments with each all-layer change.
Name: Status Register
Register: 12h
Index: Read
Bit Name
Bit # Reset Value Description
DPA_Lock
PLL_Lock
Reserved
0
N/A
N/A
0
DPA Lock Status
PLL Lock Status
Reserved
1
2-7
Bit
Name
Description
0
DPA_Lock
PLL_Lock
Reserved
DPA Lock Status. (Refer to Register 0h, bits 6 and 7.)
0 = Unlocked
1 = Locked
1
PLL Lock Status. (Refer to Register 0h, bits 6 and 7.)
0 = Unlocked
1 = Locked
2-7
ICS1524 Rev C 01/31/2003
12
ICS1524
I2C Data Characteristics
Bit transfer on the I2C-bus
START and STOP conditions
Acknowledge on the I2C-bus
These waveforms are from "The I2C-bus and how to use it," published by Philips Semiconductor.
The document can be obtained from http://www-us2.semiconductors.philips.com/acrobat/various/i2c_bus_specification_1995.pdf
ICS1524 Rev C 01/31/2003
13
ICS1524
I2C Data Format
RANDOM REGISTER WRITE PROCEDURE
S 0 1 0 0 1 1 x W A
A
A P
7 bit address
register address
Acknowledge
data
Acknowledge
STOP condition
Acknowledge
START condition
WRITE command
RANDOM REGISTER READ PROCEDURE
S 0 1 0 0 1 1 X W A
A S 0 1 0 0 1 1 X R A
7 bit address
A P
7 bit address
register address
Acknowledge
data
Repeat START
Acknowledge
STOP condition
START condition
WRITE command
Acknowledge
READ command
NO Acknowledge
SEQUENTIAL REGISTER WRITE PROCEDURE
S 0 1 0 0 1 1 X W A
A
A
A
A P
7 bit address
register address
data
Acknowledge
data
Acknowledge
Acknowledge
Acknowledge Acknowledge
START condition
WRITE command
STOP condition
SEQUENTIAL REGISTER READ PROCEDURE
S 0 1 0 0 1 1 X W A
A S 0 1 0 0 1 1 X R A
7 bit address
A
A P
7 bit address
register address
Acknowledge
data
data
Repeat START
Acknowledge
NO Acknowledge
START condition
WRITE command
Acknowledge
READ command
Acknowledge STOP condition
Direction:
From bus host to device
From device to bus host
Note:
1. All values are transmitted with the most-significant bit first and the least-significant bit last.
2. The value of the X bit equals the logic state of pin 13 (I2CADR).
3. R = READ = 1 and W = WRITE = 0
ICS1524 Rev C 01/31/2003
14
ICS1524
General Layout Guidelines
•
•
•
•
•
Use a PC board with at least four layers: one power, one ground, and two signal.
Use at least one 4.7 uF Tantalum (or similar) capacitor for global VDD bulk decoupling.
All supply voltages must be supplied from a common source and must ramp together.
Any flux or other board surface debris can degrade the performance of the external loop filter.
Ensure that the 1524 area of the board is free of contaminants.
Specific Layout Guidelines
1. Digital Supply (VDD) – Bypass pin 1 (VDD) to pin 2 (VSS) a 0.1-µF capacitor, located as close as possible to the pins. A
0.01-µF capacitor may be added for additional high frequency rejection.
2. External Loop Filter – Strongly recommended in All Designs. Locate loop filter components as close to pins 8 and 9
(EXTFIL and EXTFILRET) as possible with minimum length traces. Typical loop filter values are 6.8K Ohms for the series
resistor, 3300 pF RF-type capacitor for the series capacitor, and 33 pF for the shunt capacitor. (For details, see the Frequently
Asked Questions part of the ICS1523 Applications Guide, FAQ2 and FAQ3.)A ground isolated, surface trace can be useful to
isolate this section from the rest of the board.
3. Analog PLL Supply (VDDA) – Decouple main VDD from pin 10 (VDDA) with a series ferrite bead. Bypass the supply end of
the bead with 4.7-µF. Bypass pin 10 to pin 11 (VSSA) with a 0.1-µF capacitor. A0.01-µF capacitor may be added for additional
high frequency rejection. Locate these components as close as possible to the pins.
4. PECL Current Set Resistor – Locate PECL current-set resistor as close as possible to pin 24 (IREF). Bypass pin 24 to
ground with a 0.1-µF capacitor.
5. PECL Outputs – Implement these outputs as microstrip transmission lines. The trace widths shown are for 75 Ohm charac-
.
teristic impedance. Locate any optional series “snubbing” resistors as close as possible to the source pins. If the termination
resistors are included on-board, locate them as close as possible to the load and connect directly to the power and ground
planes.
[These termination resistors are omitted if the load device implements them internally. For details, see the ICS application
note on microstrip and striplines (1572AN1) and within the ICS1523 Applications Guide, the application note on Designing
a Custom Interface for the ICS1523 (1523AN4.)]
6. Output Driver Supply – Bypass pin 18 (VDDQ) to pin 19 (VSSQ) with a 0.1-µF capacitor, located as close as possible to the
pins. A 0.01-µF capacitor may be added for additional high frequency rejection.
7. SSTL_3 Outputs – SSTL_3 outputs can be used like conventional CMOS rail-to-rail logic or as a terminated transmission
line system at higher-output frequencies. With terminated outputs, the considerations of item 5, “PECL Outputs” apply. See
JEDEC documents JESD8-A and JESD8-8.
ICS1524 Rev C 01/31/2003
15
ICS1524
PECL Outputs
For information on using the ICS1524’s PECL output pins, please refer to Application Note 4: Designing a Custom
PECL Interface for the ICS1523
SSTL_3 Outputs
Unterminated Outputs
In the ICS1524, unterminated SSTL_3 output pins display exponential transitions similar to those of rectangular
pulses presented to RC loads. The 10-90% rise time is typically 1.6 ns, and the corresponding fall time is typically
700 ps. In turn, this asymmetry contributes to duty cycle asymmetry at higher output frequencies. In the absence of
significant load capacitance (which can further increase rise and fall time), this asymmetry is the dominant factor
determining high-frequency performance of these single-ended outputs. Typically, no termination is required either
for the LOCK/REF, FUNC, and CLK/2 outputs or for CLK outputs up to approximately 135 MHz.
Terminated Outputs
SSTL_3 outputs are intended to terminate in low impedances to reduce the effect of external circuit capacitance.
Use of transmission line techniques enables use of longer traces between source and driver without increasing ring-
ing due to reflections. Where external capacitance is minimal and substantial voltage swing is required to meet
LVTTL VIH and VOL requirements, the intrinsic rise and fall times of ICS1524 SSTL outputs are only slightly improved
by termination in a low impedance.
The ICS1524 SSTL output source impedance is typically less than 60 Ohms. Termination impedance of 100 Ohms
reduces output swing by less than 30% which is more than enough to drive a single load of LVTTL inputs.
VDD
330
Ω
Single
LVTTL
Load
SSTL-3 Output
ICS1524
150Ω
For more information on using the ICS1524’s SSTL output pins, please refer to Application Note 3: Using SSTL_3
Outputs with CMOS or LVTTL Inputs
ICS1524 Rev C 01/31/2003
16
ICS1524
Power Supply Considerations
The ICS1524 incorporates special internal power-on reset circuitry that requires no external reset signal connection. The sup-
ply voltage (VDD) must remain within the recommended operating conditions during normal operation. To reset the ICS1524,
the supply voltage at the part must be reduced below the threshold voltage (Vth) of the power-on reset circuit. The supply volt-
age must remain below that threshold voltage such that board power conditioning capacitors are drained and the proper reset
state is latched. The amount of time (td) to hold the voltage in a reset state varies with the design. However, a typical value of
10 ms should be sufficient.
Supply
Vol t age
Vmin
td
V = 1.8V
th
Absolute Maximum Ratings
VDD, VDDA, VDDQ (measured to VSS) . . . . . . . . . . . . . . . . . . 4.3V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3V to 5.5V
Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSSA – 0.3V to VDDA +0.3V
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSSQ – 0.3V to VDDQ +0.3V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Soldering Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
ESD Susceptibility* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 2 KV
(*Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation.)
ICS1524 Rev C 01/31/2003
17
ICS1524
Recommended Operating Conditions
VDD, VDDQ, VDDA (measured to VSS) . 3.0 to 3.6 V
Operating Temperature (Ambient). . . . . . 0 to +70°C
DC Supply Current
PARAMETER
Supply Current, Digital
Supply Current, Output Drivers
Supply Current, Analog
SYMBOL
IDDD
IDDQ
CONDITIONS
VDDD = 3.6V
VDDQ = 3.6V, no output drivers enabled.
VDDA = 3.6V
MIN
—
—
MAX UNITS
25
6
mA
mA
mA
IDDA
—
5
2
Digital Inputs (SDA, SCL, PDEN, EXTFB, HSYNC, OSC, I CADR)
PARAMETER
SYMBOL
CONDITIONS
MIN
2
VSS-0.3
0.2
MAX UNITS
Input High Voltage
VIH
5.5
0.8
V
V
Input Low Voltage
Input Hysteresis
VIL
0.6
V
Input High Current
Input Low Current
Input Capacitance
IIH
IIL
Cin
V = VDD
V = 0
IL
—
—
—
±10
±200
10
µA
µA
pF
IH
SDA (In Output Mode: SDA is Bidirectional)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX UNITS
0.4
IOUT = 3 mA. VOH = 6.0V maximum as
determined by the external pull-up resistor.
Output Low Voltage
VOL
V
PECL Outputs (DPACLK+, DPACLK–, CLK+, CLK -)
PARAMETER
SYMBOL
CONDITIONS
MIN
—
—
MAX UNITS
Output High Voltage
VOH
IOUT = 0
VDD
250
V
MHz
Maximum Output Frequency
Fp MAX VDDD = 3.3V
Output Low Voltage
(Note: VOL must not fall below
the level given so that the correct
value for IOUT can be
maintained.)
VOL IOUT = programmed value
1.0
—
V
SSTL-3 Outputs (DPACLK, CLK, FUNC, LOCK/REF)
PARAMETER
SYMBOL
CONDITIONS
MIN
—
MAX UNITS
Output Resistance
R
O
1 <V <2V
80
Ω
O
Maximum Output Frequency
Fs MAX VDDD = 3.3V
—
150
MHz
AC Input Characteristics
PARAMETER
HSYNC Input Frequency
OSC Input Frequency
SYMBOL
CONDITIONS
MIN
.008
.02
MAX UNITS
f
10
MHz
MHz
HSYNC
f
OSC
100
ICS1524 Rev C 01/31/2003
18
ICS1524
VCO Output Frequency and Intrinsic Jitter
700
600
500
400
300
200
100
0
100
0
Frequency (Slow: 3.0V @ 70ºC)
Frequency (Nominal: 3.3V @ 30ºC)
Frequency (Fast: 3.6V @ 0ºC)
Jitter (3.0V @ 70ºC)
Jitter (3.3V @ 30ºC)
Jitter (3.6V @ 0ºC)
Frequency
Jitter
VCO Voltage
Note: Measured with an Externally Forced Filter Voltage
ICS1524 Rev C 01/31/2003
19
ICS1524
DPA Delay-16 Element Resolution
20
18
16
14
12
10
8
50 MHz - SVGA @ 72 Hz
157.5 MHz - SXGA @ 85 Hz
6
4
2
0
16
0
4
8
12
DPA Setting
DPA Delay - 32 Element Resolution
45
40
35
30
25
20
15
10
5
25.175 MHz - VGA @ 60 Hz
78.75 MHz - XGA @ 75 Hz
0
32
0
4
8
12
16
20
24
28
DPA Setting
DPA Delay - 64 Element Resolution
90
80
70
60
50
40
30
20
10
0
12.27 MHz - NTSC
39.8 MHz - SVGA @ 60
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
DPA Setting
Note:
Maximum number of data points used for this graph.
ICS1524 Rev C 01/31/2003
20
ICS1524
t0
HSYNC
tR
REF
PECL CLK-
PECL CLK+
t3
tp
t1
t2
t8
t9
tS
t4
SSTL-CLK
tF
FUNC_OUT
t5
tDPA
t2
t3
tp
t1
PECL DPACLK-
PECL DPACLK+
tS
t4
t8
t9
SSTL-DPACLK
FUNC
tF
Typical Transition Times*
Symbol
Timing Description
Rise Fall Units
tR
tP
tS
tF
REF
2.8
1.0
1.6
1.2
1.8
1.2
0.7
1.0
ns
ns
ns
ns
PECL CLK
SSTL-CLK
FUNC_OUT
Output Timing*
Symbol
Timing Description
HSYNC to REF delay
REF to PECL clock delay
Min
Typ Max Units
t0
t1
11.3
-1.0
45
0.2
1.5
1.0
1.1
45
11.5
0.8
50
12
2.2
55
ns
ns
%
ns
ns
ns
ns
%
t2, t3 PECL clock duty cycle
t4
t5
t6
t7
PECL clock to SSTL_3 clock delay
PECL clock to FUNC_OUT delay
PECL clock to PECL/2 clock
0.75
1.9
1.3
1.4
50
1.2
2.3
1.5
1.8
55
PECL clock to SSTL_3–CLK/2 delay
t8, t9 SSTL clock duty cycle
*Note: Measured at 3.6V 0°C, 135-MHz output frequency, PECL clock lines to 75 Οηµ termination, SSTL_3 clock lines
unterminated, 20-pF load. Transition times vary based on termination.
ICS1524 Rev C 01/31/2003
21
ICS1524
24-Pin SOIC (wide body)
Ordering Information
Part/Order
Number
Marking
Package
Shipping
ICS1524M
ICS1524M
ICS1524M
SIOC-24
SIOC-24
Tubes
ICS1524MT
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
ICS1524 Rev C 01/31/2003
22
ICS1524
NOTES
ICS1524 Rev C 01/31/2003
23
ICS1524
Integrated Circuit Systems, Inc.
Corporate Headquarters:
2435 Boulevard of the Generals
P.O. Box 968
Valley Forge, PA 19482-0968
Telephone: 610-630-5300
Fax: 610-630-5399
San Jose Operations:
525 Race Street
San Jose, CA 95126-3448
Telephone: 408-297-1201
Fax:
408-925-9460
Web Site:
http://www.icst.com
ICS1524 Rev C 01/31/2003
24
相关型号：
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IDT
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