ICS162834 [ICSI]
18-Bit 3.3V Registered Buffer; 18位3.3V寄存缓冲器
| 型号： | ICS162834 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 18-Bit 3.3V Registered Buffer |
| 文件： | 总7页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems,Inc.
ICS162834
Advance Information
18-Bit 3.3V Registered Buffer
Recommended Applications:
• PC133 Registered Memory Module
Pin Configurations
• PC motherboards
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
Y1
GND
Y2
Y3
VDD
Y4
Y5
Y6
GND
Y7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
NC
A1
GND
A2
A3
VDD
A4
A5
A6
GND
A7
• Servers and workstations
• Provides complete PC133 DIMM solution with
ICSVF2509, ICSVF2510 PLL.
Product Features:
• Meets JESD 82-2 specification
• Internal series resistors to reduce switching noise
• ±12 mA device capability
Y8
Y9
A8
A9
• Low voltage operation
Y10
Y11
Y12
GND
Y13
Y14
Y15
VDD
Y16
Y17
GND
Y18
OE#
LE#
A10
A11
A12
GND
A13
A14
A15
VDD
A16
A17
GND
A18
CLK
GND
- VDD = 3.3 ± 0.3V
• 0.50 mm pitch, 56-Pin TSSOP package
Function Table1
Inputs
Outputs
OE#
H
L
LE#
CLK
X
Ax
X
L
Yx
Z
X
L
X
L
L
L
X
H
L
H
L
H
H
H
H
↑
L
L
↑
H
X
X
H
L
H
L
Y0(2)
Y0(3)
L
56-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch
Notes:
1.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition
Pin Description
2.
3.
Output level before the indicated steady-state
input conditions were established, provided that
CLK is HIGH before LE# went LOW.
Pin Names Description
OE#
CLK
LE#
Ax
Output Enable Input (Active Low)
Output level before the indicated steady-state
input conditions were established.
Clock Input
Block Diagram
Latch Enable Input
Data Input
OE#
Yx
Data Outputs
Supply Voltage
Ground
CLK
LE#
A1
VDD
GND
Y1
1D
C1
CK
To 17 Other Channels
0774—02/10/03
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS162834
Advance Information
General Description
The ICS162834 low voltage 18-bit register combines D-type latches and D-type flip-flops to allow data flow in
transparent, latched and clocked modes. Date flow is controlled by output-enable (OE#), latch enable (LE#),
and clock (CLK) inputs. The device operates in transparent mode when LE# is held low. The device operates
in clocked mode when LE# is high and CLK is toggled. Data transfers from the inputs (A[18:1]) to outputs
(Y[18:1]) on a positive edge transition of the clock. When OE# is low, the output state is enabled. When OE#
is high, the output port is in a high impedance state.
The 18-bit registered buffer is designed to operate with a 3.0V to 4.6V supply voltage.
All inputs support operation with standard LVTTL interface levels. This includes data inputs, clock inputs and
control inputs. Device outputs meet the requirements of the PC133 Registered DIMM specification. The device
functions as defined supports latched, registered and flow through modes of operations. The PC133
Specification requires only registered mode.
Package is a 56 thin shrink small-outline package as defined by JEDEC Publication, JEP95, MO-153.
0774—02/10/03
2
ICS162834
Advance Information
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . -0.5 to 4.6V
Input Voltage (VI) . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.6V
Output Voltage (VO) . . . . . . . . . . . . . . . . . . . . -0.5 to VDDQ + 0.5
Input Clamp Current (IIK) . . . . . . . . . . . . . . . . 50 mA
Output Clamp Current (IOK) . . . . . . . . . . . . . . ±50 mA
Continuous Output Current (IO) . . . . . . . . . . . ±50 mA
VDD, VDDQ or GND Current/Pin . . . . . . . . . . . ±100 mA
Package Thermal Impedance, OJA . . . . . . . . . . . 64°C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Recommended Operating Conditions
DESCRIPTION
Supply Voltage
Voltage Applied to input pins
PARAMETER
MIN
3.0
-0.3
0
TYP
3.3
MAX
3.6
VDD
VIN
3.6
Outputs enabled
Outputs high-Z
Voltage Applied to
output or I/O pins
VDD
VDD
70
VOUT
TA
0
Operating free-air temperature
0
Switching Characteristics
VCC = 3.3V ± 0.15V
Symbol
Parameter
UNITS
MIN
MAX
Propagation Delay CLK to
Yx
t
PLH, tPHL
1.8
3.5
ns
tSK(0)
Output Skew*
-
500
-
ps
fCLOCK
150
MHz
* Skew between any two putputs of the same package and switching in the
same direction
0774—02/10/03
3
ICS162834
Advance Information
Electrical Characteristics - DC
TA = 0 - 70° C; VDD = 3.3 ± 0.3V, VDDQ=3.3 ± 0.3V; (unless otherwise stated)
SYMBOL
VIH
PARAMETERS
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
Low-level output voltage
Input leakage current
CONDITIONS
VDD (V)
3.0 - 3.6
3.0 - 3.6
3.0
MIN
2.0
TYP MAX UNITS
V
VIL
0.8
V
V
VOH
VOL
II
IOH = -12 mA, VIH = 2.0V
IOL = 12 mA, VIL = 0.8V
VI = VDD or GND
2.2
3.0
0.8
±10
±20
3.0 - 3.6
µA
µA
IOZ
Off-state leakage current
VO = VDD or GND#, OE = VDD
IDD
Quiescent Supply Current
VI = VDD or GND, IO = 0
±40
µA
* Parameters are characterized over recommended operating conditions.
Critical Register Specifications*
SYMBOL
PARAMETERS
CONDITION
VDD (V)
MIN
TYP
4.0
MAX
3.5
UNITS
tPD**
Propagation Delay (CK to Y)
Propagation Delay (CK to Y)
Setup time (A before CK)
Hold time (A after CK)
RL = 500 Ω, CL = 50 pF
RL = 500 Ω, CL = 30 pF
3.0 - 3.6
3.0 - 3.6
3.0 - 3.6
3.0 - 3.6
1.4
0.7
1.0
0.6
ns
ns
ns
ns
t
PD**
tS
2.5
tH
CI
Clock input capacitance
3.0 - 3.6
3.3
6.0
pF
* Parameters are characterized over recommended operating conditions.
** The tPD value in this table would equate to the 'Time-to-Vm' delay described in the post register timing specifications of the
PC133 registered DIMM Specification. The first value applies to DIMMs with nine SDRAM loads per register output, and the
second to DIMMs with eighteen SDRAM loads per register output. These values should serve as only an initial starting point,
0774—02/10/03
4
ICS162834
Advance Information
Test Circuit and Switching Waveforms
2 x V
DD
Open
GND
R
R
L
Pulse
Generator
DUT
R
C
L
T
L
Test Circuit
Test circuit component values:
RL = Load Resistor = 500 Ω
CL = Load Capacitance and includes probe and jig capacitance
RT = Termination resistance should be equal to ZOUT of Pulse Generator
VIN = 0 to V
DD
tr = tf 2.0 ns (10% to 90%) unless otherwise specified.
Parameter Tested Switch Position
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Open
Open
GND
2 x VDD
GND
2 x VDD
0774—02/10/03
5
ICS162834
Advance Information
PROPAGATION DELAY MEASUREMENT
SETUP TIME MEASUREMENTS
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
A
A
n
n
t
t
S
S
IH
IL
IH
IL
CK
CK
t
t
PHL
PLH
OH
OL
OH
OL
Y
Y
n
n
HOLD TIME MEASUREMENTS
ENABLE AND DISABLE TIMES
DISABLE
ENABLE
V
V
IH
T
V
IH
IL
CONTROL
INPUT
A
n
V
0V
t
PZL
t
PLZ
t
t
H
H
V
V
V
V
IH
IL
V
LOAD/2
V
LOAD/2
OUTPUT
NORMALLY
LOW
CK
SWITCH
CLOSED
V
T
V
V
LZ
OL
t
PHZ
t
PZH
OH
OL
OUTPUT
NORMALLY
HIGH
V
V
OH
HZ
Y
n
SWITCH
OPEN
V
T
0V
0V
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
tSK(X)
OUTPUT SKEW -
PULSE WIDTH
V
V
IH
T
LOW-HIGH-LOW
V
T
INPUT
PULSE
0V
t
PLH1
t
PHL1
V
OH
t
W
V
T
HIGH-LOW-HIGH
PULSE
V
T
OUTPUT 1
OUTPUT 2
V
OL
t
SK (x)
t
SK (x)
V
OH
V
V
T
OL
t
PLH2
t
PHL2
t
SK(x) = tPLH2
-
t
PLH1 or
t
PHL2
-
tPHL1
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
Switching Waveforms
0774—02/10/03
6
ICS162834
Advance Information
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
E1
E
INDEX
AREA
c
1
2
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
a
D
E1
e
6.00
6.20
.236
0.020 BASIC
.244
0.50 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
A
A2
0°
--
8°
0.10
0°
--
8°
.004
α
aaa
A1
- C -
VARIATIONS
e
SEATING
PLANE
b
D mm.
D (inch)
N
MIN
MAX
14.10
MIN
.547
MAX
.555
aaa
C
56
13.90
Reference Doc.: JEDEC Publication 95, M O-153
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
10-0039
(240 mil)
Ordering Information
ICS162834AG-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
DeviceType (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0774—02/10/03
7
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