ICS2572N [ICSI]
User-Programmable Dual High-Performance Clock Generator; 用户可编程双通道高性能时钟发生器
| 型号： | ICS2572N |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | User-Programmable Dual High-Performance Clock Generator |
| 文件： | 总10页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS2572
Integrated
Circuit
Systems, Inc.
User-Programmable Dual High-Performance Clock Generator
Description
Features
The ICS2572 is a dual-PLL (phase-locked loop) clock gener-
ator with differential video outputs specifically designed for
high-resolution, high-refresh rate, video applications. The
video PLL generates any of 16 pre-programmed frequencies
through selection of the address lines FS0-FS3. Similarly, the
auxiliary PLL can generate any one of four pre-programmed
frequencies via the MS0 & MS1 lines.
•
Advanced ICS monolithic phase-locked loop
technology
Supports high-resolution graphics - differential CLK out-
put to 185 MHz
Divided dotclock output (LOAD) available
Simplified device programming
Sixteen selectable VCLK frequencies (all user
re-programmable)
Four selectable MCLK frequencies (all user
re-programmable)
•
•
•
•
A unique feature of the ICS2572 is the ability to redefine
frequency selections after power-up. This permits complete
set-up of the frequency table upon system initialization.
•
•
Windows NT compatible
Applications
•
High end PC/low end workstation graphics designs
requiring differential output
•
X Terminal graphics
Block Diagram
XTAL1
Crystal
Oscillator
Reference
Divider
/1, 4, 5 or 8
EXTFREQ
LOAD
XTAL2
/ 2
/ 4
/ 8
Phase-
Frequency
Comparator
Charge
Pump
VCO
CLK+
CLK-
Prescaler
/ M
/ A
MCLK PLL (as above)
/ 2
Strobe
FS0
FS1
FS2
MCLK
VCLK Set &
Program
Mode
/ 4
/ 8
Interface
FS3
MCLK Set
MS0
MS1
ICS2572RevC090894
E-95
ICS2572
Pin Configuration
XTAL1
XTAL2
XTFREQ
FS0
1
2
20
19
18
17
16
15
14
13
12
11
VDD
CLK+
CLK-
VSS
3
4
FS1
5
LOAD
VAA
STROBE
FS2
6
7
VSS
FS3
8
VDD
MCLK
MS1
MS0
9
VSS
10
20-Pin DIP or SOIC
J-4, J-7
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
Quartz crystal connection 1/Reference Frequency Input.
Quartz crystal connection 2.
1
2
3
4
5
7
8
6
9
XTAL1
XTAL2
EXTFREQ
FS0
FS1
FS2
FS3
STROBE
MS0
MS1
CLK+
CLK-
LOAD
MCLK
RESERVED
VSS
VDD
VAA
A
A
I
I
I
I
I
I
I
External Frequency Input
VCLK PLL Frequency Select LSB.
VCLK PLL Frequency Select Bit.
VCLK PLL Frequency Select Bit.
VCLK PLL Frequency Select MSB.
Control for Latch of VCLK Select Bits (FS0-FS3).
MCLK PLL Frequency Select LSB.
MCLK PLL Frequency Select MSB.
Pixel Clock Output (not inverted)
Pixel Clock Output (inverted)
Divided Dotclock (/4, 5, or 8)
MCLK Frequency Output
Must Be Connected to VSS.
Device Ground. All pins must be connected.
Output Stage Vdd. All pins must be connected.
Synthesizer Vdd.
11
19
18
16
12
17
10, 14
13, 20
15
I
O
O
O
O
-
P
P
P
E-96
ICS2572
FS0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FS1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FS2
FS3
Digital Inputs
START bit (must be “0”)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
The FS0-FS3 pins and the STROBE pin are used to select the
desired operating frequency of the VCLK output from the 16
pre-programmed/user-programmed selections in the ICS2572.
These pins are also used to load new frequency data into the
registers.
”
R/W* control
”
L0 (location LSB)
”
Available configurations for the STROBE input include: posi-
tive-edge triggered, negative-edge triggered, high-level trans-
parent, and low-level transparent (see Ordering Information).
L1
”
L2
”
L3
VCLK Output Frequency Selection
”
To change the VCLK output frequency, simply write the ap-
propriate data to the ICS2572 FS inputs. Do not perform any
further writes to the device for 50 milliseconds (assumes a
14.318 MHz reference). The synthesizer will output the new
frequency programmed into that location after a brief delay
(see timeout specifications).
L4 (location MSB)
”
N0 (feedback LSB)
”
N1
”
N2
”
MCLK Output Frequency Selection
N3
The MS0-MS1 pins are used to directly select the desired
operating frequency of the MCLK output from the four pre-
programmed/user-programmed selections in the ICS2572.
These inputs are not latched, nor are they involved with mem-
ory programming operations.
”
N4
”
N5
”
N6
Programming Mode Selection
A programming sequence is defined as a period of at least 50
milliseconds of no data writes to the ICS2572 (to clear the shift
register) followed by a series of data writes (as shown here):
”
N7 (feedback MSB)
”
EXTFREQ bit (selected if “1”)
”
D0 (post-divider LSB)
”
D1 (post-divider MSB)
”
STOP1 bit (must be “1”
”
STOP2 bit (must be “1”)
”
E-97
ICS2572
Observe that the internal shift register is “clocked” by a tran-
sition of FS3 data from “0” to “1.” If an extended sequence of
register loading is to be performed (such as a power-on initiali-
zation sequence), note that it is not necessary to implement the
50 millisecond delay between them. Simply repeat the se-
quence above as many times as desired. Writes to the FS port
will not be treated as frequency select data until up to 50
milliseconds have transpired since the last write. Note that FS0
and FS1 inputs are “don’t care.”
Table 2 - Post-Divider Programming
D[1-0]
00
POST-DIVIDER
9
4
2
1
01
10
11
Read/Write* Control Bit
Data Description
When set to a “0,” the ICS2572 shift register will transfer its
contents to the selected memory register at the completion of
the programming sequence outlined above.
Location Bits (L0-L4)
The first five bits after the start bit control the frequency
location to be re-programmed according to this table. The
rightmost bit (the LSB) of the five shown in each selection of
the table is the first one sent.
When this bit is a “1,” the selected memory location will be
transferred to the shift register to permit a subsequent readback
of data. No modification of device memory will be performed.
Table 1 - Location Bit Programming
To readback any location of memory, perform a “dummy”
write of data (complete with start and stop bits) to that location
but set the R/W* control bit (make it “1”). At the end of the
sequence (i.e., after the stop bits have been “clocked”), “clock-
ing” of the FS3 input 11 more times will output the data bits
only in the same sequence as above on the FS0 pin.
L[4-0]
01100
01101
01110
01111
10010
10011
LOCATION
VCLK Address 12
VCLK Address 13
VCLK Address 14
VCLK Address 15
MCLK Address 2
MCLK Address 3
EXTFREQ Input
TheEXTFREQ inputallows anexternallygeneratedfrequency
to be routed to the VCLK output pin under device program-
ming control. If the EXTFREQ bit is set (logic “1”) at the
selected address location (VCLK addresses only), the fre-
quency applied to the EXTFREQ input will be routed to the
VCLK output.
Feedback Set Bits (N0-N7)
These bits control the feedback divider setting for the location
specified. The modulus of the feedback divider will be equal
to the value of these bits + 257. The least significant bit (N0)
is sent first.
Post-Divider Set Bits (D0-D1)
These bits control the post-divider setting for the location
specified according to this table. The least significant bit (D0)
is sent first.
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ICS2572
The VCO will then need to be programmed to two times
45.723 MHz, or 91.446 MHz. To calculate the required feed-
back divider modulus we divide the VCO frequency by the
reference frequency and multiply by the reference divider:
Frequency Synthesizer Description
Refer to Figure 1 for a block diagram of the ICS2572.
The ICS2572 generates its output frequencies using phase-
locked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
to be ratiometrically related to the reference frequency pro-
vided to the PLL. The phase-frequency detector shown in the
block diagram drives the VCO to a frequency that will cause
the two inputs to the phase-frequency detector to be matched
in frequency and phase. This occurs when:
91.446
*43=274.62
14.31818
which we round off to 275. The exact output frequency will
be:
275
43
1
*14.31818* =45.784 MHz
2
N
2
The value of the N programming bits may be calculated by
subtracting 257 from the desired feedback divider modulus.
Thus, the N value will be set to 18 (275-257) or 000100102.
The D bit programming is 102 (from Table 2).
F
=F
VCO
*
XTAL1
where N is the effective modulus of the feedback divider chain
and R is the modulus of the reference divider chain.
The feedback divider on the ICS2572 may be set to any integer
value from 257 to 512. This is done by the setting of the N0-N7
bits. The standard reference divider on the ICS2572 is fixed to
a value of 43 (this may be set to a different value via ROM
programming; contact factory). The ICS2572 is equipped with
a post-divider and multiplexer thatallows the output frequency
range to be scaled down from that of the VCO by a factor of 2,
4, or 8.
LOAD Frequency Selection
The LOAD (or divided dotclock) output frequency will be the
CLK+/CLK- frequency divided by 1, 4, 5, or 8. The choice of
modulus is a factory option, and is specified along with the
ROM frequencies in the VCLK and MCLK tables by way of
the two-digit suffix of the part number.
Therefore, the VCO frequency range will be from 5.976 to
11.906 (257/43 to 512/43) of the reference frequency. The
output frequency range will be from 0.747 to 11.906 times the
reference frequency. Worst case accuracy for any desired fre-
quency within that range will be 0.2%.
Reference Oscillator & Crystal
Selection
The ICS2572 has on-board circuitry to implement a Pierce
oscillator with the addition of only one external component, a
quartz crystal. Pierce oscillators operate the crystal in parallel-
resonant (also called anti-resonant mode. See the AC Charac-
teristics for the effective capacitive loading to specify when
ordering crystals.
If a 14.31818 MHz reference is used, the output frequency
range would be from 10.697 MHz to 170.486 MHz.
Programming Example
Suppose that we want differential CLK output to be
45.723 MHz. We will assume the reference frequency to be
14.31818 MHz.
Crystals characterized for their series-resonant frequency may
also be used with the ICS2572. Be aware that the oscillation
frequency in circuit will be slightly higher than the frequency
that is stamped on the can (typically 0.025-0.05%).
The VCO frequency range will be 85.565 MHz to
170.486 MHz (5.976 * 14.31818 to 11.906 * 14.31818). We
will need to set the post-divider to two to get an output of
45.723 MHz.
As the entire operation of the phase-locked loop depends on
having a stable reference frequency, we recommend that the
crystal bemounted as closely as possible to the package. Avoid
routing digital signals or the ICS2572 outputs underneath or
near these traces. It is also desirable to ground the crystal can
to the ground plane, if possible.
E-99
ICS2572
External Reference Sources
An external frequency source may be used as the reference for
the VCLK and MCLK PLLs. To implement this, simply con-
nect the reference frequency source to the XTAL1 pin of the
ICS2572. For best results, insure that the clock edges are as
clean and fast as possible and that the input voltage thresholds
are not violated.
Power Supply
TheICS2572has twoVSS pins to reduce theeffects of package
inductance. Both pins are connected to the same potential on
the die (the ground bus). BOTH of these pins should connect
to the ground plane of the video board as close to the package
as is possible.
The ICS2572 has a VDD pin which is the supply of +5 volt
power to all output stages. This pin should be connected to the
power plane (or bus) using standard high-frequency decou-
pling practice. That is, use low-capacitors should have low
series inductance and be mounted close to the ICS2572.
The VAA pin is the power supply for the synthesizer circuitry
and other lower current digital functions. We recommend that
RC decoupling or zener regulation be provided for this pin (as
shown in the recommended application circuitry). This will
allow the PLL to “track” through power supply fluctuations
without visible effects.
E-100
ICS2572
Absolute Maximum Ratings
Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -.5V to +7V
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-.5V to VDD +.5V
Ambient operating temp . . . . . . . . . . . . . . . . . . . . . . . 0 to 70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -85 to + 150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
DC Characteristics
PARAMETER
TTL-Compatible Inputs
(FS0-3, MS0-1, STROBE):
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Capacitance
XTAL1:
SYMBOL
TEST CONDITIONS
MIN
-
-
2.0
TYP
MAX
-
-
UNITS
-
-
-
-
-
-
-
-
-
-
-
Vih
Vil
Iih
Iil
Cin
VDD+0.5
V
V
uA
uA
pF
VSS-0.5
0.8
10
200
8
-
-
-
-
-
Input High Voltage
Input Low Voltage
CLK+/CLK- Output
Sink Current
Vxh
Vxl
Isink
VDD*0.75
VSS-0.5
-
VDD+0.5
VDD*0.25
-
V
V
mA
High Voltage (Other
Outputs)
Voh
4
-
-
V
@Ioh=0.4mA
Low Voltage (Other
Outputs)
-
-
-
-
-
0 .4
Vo l
V
@Iol=8.0mA
-
-
-
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ICS2572
AC Characteristics
PARAMETER
Phase-Locked Loop:
VCLK, MCLK VCO
Frequency
PLLAcquire Time
Crystal Oscillator
SYMBOL
TEST CONDITIONS
MIN
-
100
TYP
-
-
MAX
-
235
UNITS
Fvco
MHz
uSec
Tlock
-
-
5
500
-
-
-
-
25
Crystal Frequency
Range
Parallel Loading
Capacitance
XTAL1 Minimum High
Time
XTAL1 Minimum Low
Time
Fxtal
MHz
pF
-
20
-
-
-
-
Txhi
Txlo
8
8
ns
-
ns
Power Supplies:
-
-
-
-
50
-
-
-
-
-
-
35
10
-
-
VDD Supply Current
VAA Supply Current
Digital Outputs:
idd
Iaa
mA
mA
CLK+/CLK- Recom-
mended Termination
Other Outputs Rise
Time @ Cload=20pF
Other Outputs Fall Time
@ Cload=20pF
2
ohms
ns
Tf
Tf
-
-
-
-
2
-
ns
E-102
ICS2572
PATTERN
Reference Divider
ICS2572-01
43
VCLK ADDR
FbkDiv/PostDiv - FVCLK(MHz)
300/1- 99.89
0
1
2
3
4
5
6
378/1 - 125.87
277/1 - 92.24
432/4 - 35.96
302/2 - 50.28
340/2 - 56.61
EXTFREQ-
7
8
9
A
B
C
D
E
270/2 - 44.95
405/1 - 134.86
384/4 - 31.97
330/1 - 109.88
481/2 - 80.08
479/4 - 39.87
270/2 - 44.95
450/2 - 74.92
390/2 - 64.93
FbkDiv/PostDiv - FMCLK
481/4 - 40.04
270/2 - 44.95
396/4 - 32.97
300/2 - 49.95
F
MCLK ADDR
0
1
2
3
Ordering Information
ICS2572N-SXX or ICS2572M-SXX (0.300" DIP or SOIC Package)
Example:
ICS XXXX N-SXX
S=Strobe Option/XX=Default Frequencies
Package Type
N=DIP (Plastic)
M=SOIC
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device; GSP=Genlock Device
Where:
“s” denotes strobe option:
A - positive level transparent (i.e., 2494 interface compatible)
“xx” denotes default frequencies: B - negative level transparent
C - positive edge triggered
D - negative edge triggered
E-103
ICS2572
NOTES
E-104
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