ICS345 [ICSI]
Triple PLL Field Programmable SS VersaClock Synthesizer; 三重PLL现场可编程SS VersaClock合成
| 型号： | ICS345 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Triple PLL Field Programmable SS VersaClock Synthesizer |
| 文件： | 总7页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS345
Triple PLL Field Programmable SS VersaClock Synthesizer
Description
Features
• Packaged as 20-pin SSOP (QSOP)
• Spread spectrum capability
The ICS345 field programmable clock synthesizer
generates up to nine high-quality, high-frequency clock
outputs including multiple reference clocks from a
low-frequency crystal or clock input. It is designed to
replace crystals and crystal oscillators in most
electronic systems.
• Eight addressable registers
• Replaces multiple crystals and oscillators
• Output frequencies up to 200 MHz at 3.3 V
• Input crystal frequency of 5 to 27 MHz
• Input clock frequency of 2 to 50 MHz
• Up to nine reference outputs
TM
Using ICS’ VersaClock software to configure PLLs
and outputs, the ICS345 contains a One-Time
Programmable (OTP) ROM to allow field
programmability. Programming features include eight
selectable configuration registers, up to two sets of four
low-skew outputs, and optional Spread Spectrum
outputs.
• Up to two sets of four low-skew outputs
• Operating voltages of 3.3 V
• Advanced, low-power CMOS process
• For one output clock, use the ICS341. For two output
clocks, see the ICS342. For three output clocks, see
the ICS343. For more than three outputs, see the
ICS345 or ICS348.
Using Phase-Locked Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace multiple
crystals and oscillators, saving board space and cost.
• Available in Pb (lead) free packaging
The ICS345 is also available in factory programmed
custom versions for high-volume applications.
Block Diagram
3
VDD
PLL1 with
Spread
Spectrum
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
3
OTP
S2:S0
ROM
with
PLL
Divide
Logic
and
Output
Enable
Control
Values
PLL2
PLL3
Crystal or
clock input
X1/ICLK
Crystal
Oscillator
X2
GND
2
External capacitors are
required with a crystal input.
PDTS
MDS 345 D
1
Revision 090704
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS345
Triple PLL Field Programmable SS VersaClock Synthesizer
Pin Assignment
X1/ICLK
S0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
X2
VDD
PDTS
S2
S1
CLK9
VDD
GND
CLK1
CLK2
CLK3
CLK4
VDD
GND
CLK5
CLK6
CLK7
CLK8
20-pin (150 mil) SSOP (QSOP)
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
2
X1/ICLK
S0
XI
Crystal input. Connect this pin to a crystal or external input clock.
Select pin 0. Internal pull-up resistor.
Input
Input
3
S1
Select pin 1. Internal pull-up resistor.
4
CLK9
VDD
GND
CLK1
CLK2
CLK3
CLK4
CLK8
CLK7
CLK6
CLK5
GND
VDD
S2
Output Output clock 9. Weak internal pull-down when tri-state.
Connect to +3.3 V.
Connect to ground.
5
Power
Power
6
7
Output Output clock 1. Weak internal pull-down when tri-state.
Output Output clock 2. Weak internal pull-down when tri-state.
Output Output clock 3. Weak internal pull-down when tri-state.
Output Output clock 4. Weak internal pull-down when tri-state.
Output Output clock 8. Weak internal pull-down when tri-state.
Output Output clock 7. Weak internal pull-down when tri-state.
Output Output clock 6. Weak internal pull-down when tri-state.
Output Output clock 5. Weak internal pull-down when tri-state.
8
9
10
11
12
13
14
15
16
17
Power
Power
Input
Connect to ground.
Connect to +3.3 V.
Select pin 2. Internal pull-up resisitor.
Power-down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resisitor.
18
PDTS
Input
Connect to +3.3 V.
19
20
VDD
X2
Power
XO
Crystal Output. Connect this pin to a crystal. Float for clock input.
MDS 345 D
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Revision 090704
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS345
Triple PLL Field Programmable SS VersaClock Synthesizer
spaces, instead they should be separated and away
from other traces.
External Components
Series Termination Resistor
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers.
ICS345 Configuration Capabilities
The architecture of the ICS345 allows the user to easily
configure the device to a wide range of output
frequencies, for a given input reference frequency.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS345 must be isolated from system power supply
noise to perform optimally.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
set within the range of M = 1 to 2048 and N = 1 to 1024.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
Crystal Load Capacitors
The ICS345 also provides separate output divide
values, from 2 through 20, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
Each output frequency can be represented as:
REFFreq
OutputDivide
M
-------------------------------------- ----
OutputFreq =
⋅
N
ICS VersaClock Software
The value (in pF) of these crystal caps should equal
ICS applies years of PLL optimization experience into a
user friendly software that accepts the user’s target
reference clock and output frequencies and generates
the lowest jitter, lowest power configuration, with only a
press of a button. The user does not need to have prior
PLL experience or determine the optimal VCO
(C -6 pF)*2. In this equation, C = crystal load
L
L
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
frequency to support multiple output frequencies.
PCB Layout Recommendations
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and
provides an easy to understand, bar code rating for the
target output frequencies. The user may evaluate
output accuracy, performance trade-off scenarios in
seconds.
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via.
Spread Spectrum Modulation
The ICS345 utilizes frequency modulation (FM) to
distribute energy over a range of frequencies. By
modulating the output clock frequencies, the device
effectively lowers energy across a broader range of
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
MDS 345 D
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Revision 090704
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS345
Triple PLL Field Programmable SS VersaClock Synthesizer
frequencies; thus, lowering a system’s electromagnetic
interference (EMI). The modulation rate is the time from
transitioning from a minimum frequency to a maximum
frequency and then back to the minimum.
be modulated between +/- 0.125% to +/-2.0%. For
down spread, the frequency can be modulated
between -0.25% to -4.0%.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates,
if a common VCO frequency can be identified.
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is
equal in the positive and negative directions. The
effective average frequency is equal to the target
frequency. In applications where the clock is driving a
component with a maximum frequency rating, down
spread should be applied. In this case, the maximum
frequency, including modulation, is the target
frequency. The effective average frequency is less than
the target frequency.
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to
the output clock frequency may occur at a variety of
rates. For applications requiring the driving of
“down-circuit” PLLs, Zero Delay Buffers, or those
adhering to PCI standards, the spread spectrum
modulation rate should be set to 30-33 kHz. For other
applications, a 120 kHz modulation option is available.
The ICS345 operates in both center spread and down
spread modes. For center spread, the frequency can
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS345. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Parameter
Condition
Min.
Typ.
Max.
7
Units
V
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
-0.5
-0.5
-65
VDD+0.5
VDD+0.5
150
V
Clock Outputs
V
Storage Temperature
Soldering Temperature
Junction Temperature
°C
°C
°C
Max 10 seconds
260
125
MDS 345 D
4
Revision 090704
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS345
Triple PLL Field Programmable SS VersaClock Synthesizer
Recommended Operation Conditions
Parameter
Min.
0
Typ.
Max.
+70
+85
+3.45
4
Units
°C
Ambient Operating Temperature (ICS345RP)
Ambient Operating Temperature (ICS345RIP)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
-40
°C
+3.15
+3.3
V
ms
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85°C
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Operating Voltage
VDD
3.15
3.45
V
Configuration Dependent -
See VersaClock
mA
TM
Estimates
Operating Supply Current
Input High Voltage
IDD
Nine 33.3333 MHz outs,
PDTS = 1, no load, Note 1
23
20
mA
PDTS = 0, no load, Note 1
S2:S0
µA
V
Input High Voltage
V
2
IH
Input Low Voltage
V
S2:S0
0.4
0.4
V
V
V
V
V
V
IL
Input High Voltage, PDTS
Input Low Voltage, PDTS
Input High Voltage
V
VDD-0.5
VDD/2+1
IH
V
IL
V
ICLK
ICLK
IH
Input Low Voltage
V
VDD/2-1
IL
Output High Voltage
(CMOS High)
V
I
= -4 mA
VDD-0.4
2.4
OH
OH
Output High Voltage
Output Low Voltage
Short Circuit Current
V
I
I
= -12 mA
= 12 mA
V
V
OH
OH
V
0.4
OL
OL
I
70
mA
Ω
OS
Nominal Output
Impedance
Z
20
O
Internal pull-up resistor
R
S2:S0, PDTS
CLK outputs
250
525
kΩ
kΩ
PUS
Internal pull-down
resistor
R
PD
Input Capacitance
C
Inputs
4
pF
IN
Note 1: Example with 25 MHz crystal input with nine outputs of 33.3 MHz, no load, and VDD = 3.3 V.
MDS 345 D
5
Revision 090704
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS345
Triple PLL Field Programmable SS VersaClock Synthesizer
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Fundamental crystal
Input clock
Min.
5
Typ.
Max. Units
Input Frequency
F
27
50
MHz
MHz
MHz
ns
IN
2
Output Frequency
Output Rise Time
Output Fall Time
Duty Cycle
VDD=3.3 V
0.25
200
t
20% to 80%, Note 1
80% to 20%, Note 1
Note 2
1
1
OR
t
ns
OF
40
49-51
4
60
10
%
PLL lock-time from
power-up, Note 3
ms
Power-up time
PDTS goes high until
stable CLK output,
Spread Spectrum Off,
Note 3
0.2
2
ms
ms
PDTS goes high until
stable CLK output,
Spread Spectrum On,
Note 3
4
7
One Sigma Clock Period Jitter
Maximum Absolute Jitter
Configuration
Dependent
50
ps
ps
t
Deviation from Mean.
Configuration
+200
ja
Dependent
Pin-to-Pin Skew
Low Skew Outputs
-250
250
ps
Note 1: Measured with 15pF load
Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%
Note 3: ICS test mode output occurs for first 170 clock cycles on CLK7 for each PLL powered up. PDTS
transition high on select address change.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
Still air
135
93
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
78
Thermal Resistance Junction to Case
θ
60
MDS 345 D
6
Revision 090704
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS345
Triple PLL Field Programmable SS VersaClock Synthesizer
Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Wide Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
20
Symbol
Min
Max
1.75
0.25
1.50
0.30
0.25
8.75
6.20
4.00
Min
Max
A
A1
A2
b
1.35
0.10
--
0.20
0.18
8.55
5.80
3.80
0.053
0.004
--
0.008
0.007
0.337
0.228
0.150
0.069
0.010
0.059
0.012
0.010
0.344
0.244
0.157
E1
E
INDEX
AREA
c
D
E
E1
e
1
2
.635 Basic
.025 Basic
D
L
0.40
0°
1.27
8°
0.016
0°
0.050
8°
α
aaa
--
0.10
--
0.004
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
Marking
Shipping
packaging
Package
Temperature
ICS345RP
ICS345RIP
ICS345RLF
ICS345RP
ICS345RIP
Tubes
20-pin SSOP
20-pin SSOP
20-pin SSOP
0 to +70°C
-40 to +85°C
0 to +70°C
Tubes
ICS345RLF
Tubes
“LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 345 D
7
Revision 090704
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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