ICS40004A11L [ICSI]
FEMTOCLOCKS? CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER; FEMTOCLOCKS⑩ CRYSTAL -TO LVCMOS / LVTTL频率合成器
| 型号： | ICS40004A11L |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER |
| 文件： | 总10页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS840004-11
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
• Four LVCMOS/LVTTL outputs, 15Ω typical output imped-
The ICS840004-11 is a 4 output LVCMOS/
ICS
HiPerClockS™
ance
LVTTL Synthesizer optimized to generate
Ethernet reference clock frequencies and is a
member of the HiPerClocksTM family of high
performance clock solutions from ICS. Using a
• Crystal oscillator interface
• Input frequency range: 22.4MHz to 28MHz
• Output frequency Range: 56MHz - 140MHz
• VCO Range: 560MHz - 700MHz
25MHz, 18pF parallel resonant crystal, 125MHz and
62.5MHz can be generated based on one frequency select
pin (F_SEL). The ICS840004-11 uses ICS’ 3rd generation low
phase noise VCO technology and can achieve 1ps or lower
typical random rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS840004-11 is packaged in a small
20-pin TSSOP package.
• RMS phase jitter at 125MHz (1.875MHz - 20MHz):
0.70ps (typical)
• RMS phase noise at 125MHz:
• Full 3.3V supply
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
FREQUENCY SELECT FUNCTION TABLE FOR ETHERNET FREQUENCIES
Inputs
M Divider N Divider
Output Frequency
(25MHz Ref.)
M/N
Ratio Value
F_SEL
Value
Value
0
1
25
10
2.5
62.5
125
25
5
5
BLOCK DIAGRAM
PIN ASSIGNMENT
F_SEL
nc
nc
1
20
19
18
17
16
15
14
13
12
11
GND
Q0
Q1
VDDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
2
3
4
5
6
7
8
9
Pullup
OE
nc
nc
OE
nc
nc
VDDA
nc
VDD
Pullup
F_SEL
F_SEL
N
25MHz
XTAL_IN
Q0
Q1
Phase
Detector
0
1
÷10
VCO
OSC
÷5
10
XTAL_OUT
ICS840004-11
Q2
Q3
20-LeadTSSOP
M = ÷25 (fixed)
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
840004AG-11
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REV.A OCTOBER 3, 2005
1
PRELIMINARY
ICS840004-11
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
F_SEL
Input
Pullup
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
2, 3, 4, 6,
7, 9, 20
nc
Unused
Input
No connect.
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
5
OE
8
VDDA
VDD
Power
Power
Analog supply pin.
Core supply pin.
10
11,
12
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Input
Power
Output
Power
13, 19
GND
Power supply ground.
14, 15
17, 18
Q3, Q2,
Q1, Q0
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
15Ω typical output impedence.
Output supply pin.
16
VDDO
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
TBD
51
pF
pF
kΩ
Ω
CPD
Power Dissipation Capacitance
Input Pullup Resistor
VDD, VDDA, VDDO = 3.465V
RPULLUP
ROUT
Output Impedance
15
840004AG-11
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REV.A OCTOBER 3, 2005
2
PRELIMINARY
ICS840004-11
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
3.3
3.3
90
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.135
3.135
V
mA
mA
mA
IDDA
IDDO
8
5
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
Input High Voltage
2
VDD + 0.3
V
VIL
IIH
Input Low Voltage
-0.3
0.8
5
V
µA
µA
V
Input High Current OE, F_SEL
Input Low Current OE, F_SEL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
VDDO = 3.3V 5ꢀ
IIL
-150
2.6
VOH
VOL
VDDO = 3.3V 5ꢀ
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Fundamental
25
Typical Maximum Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
840004AG-11
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REV.A OCTOBER 3, 2005
3
PRELIMINARY
ICS840004-11
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, VDD =VDDA =VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency Range
56
140
MHz
ps
tsk(o)
Output Skew; NOTE 1, 2
25
125MHz @ Integration Range:
1.875MHz - 20MHz
62.5MHz @ Integration Range:
1.875MHz - 20MHz
0.70
ps
ps
RMS Phase Jitter (Random);
NOTE 3
tjit(Ø)
0.54
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
470
50
ps
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
840004AG-11
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REV.A OCTOBER 3, 2005
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PRELIMINARY
ICS840004-11
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 62.5MHZ @3.3V
0
-10
-20
1Gb Ethernet Filter
-30
-40
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.54ps
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
Raw Phase Noise Data
Phase Noise Result by adding
1Gb Ethernet Filter to raw data
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 125MHZ @2.5V
0
-10
-20
1Gb Ethernet Filter
-30
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.70ps
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
Raw Phase Noise Data
-150
-160
-170
Phase Noise Result by adding
1Gb Ethernet Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
840004AG-11
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REV.A OCTOBER 3, 2005
5
PRELIMINARY
ICS840004-11
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
VDDO
2
SCOPE
VDD
VDDA, VDDO
,
Qx
Qy
Qx
LVCMOS
VDDO
2
GND
tsk(o)
-1.65V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Phase Noise Plot
VDDO
2
Q0:Q3
tPW
tPERIOD
Phase Noise Mask
tPW
x 100ꢀ
odc =
tPERIOD
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
RMS PHASE JITTER
80ꢀ
tF
80ꢀ
tR
20ꢀ
20ꢀ
Clock
Outputs
OUTPUT RISE/FALL TIME
840004AG-11
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REV.A OCTOBER 3, 2005
6
PRELIMINARY
ICS840004-11
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS840004-11 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840004-11 has been characterized with 18pF paral- below were determined using a 25MHz 18pF parallel reso-
lel resonant crystals.The capacitor values shown in Figure 2 nant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVCMOS OUTPUT:
For applications not requiring the use of the crystal oscillator All unused LVCMOS output can be left floating. We
input, both XTAL_IN and XTAL_OUT can be left floating. recommend that there is no trace attached.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
840004AG-11
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REV.A OCTOBER 3, 2005
7
PRELIMINARY
ICS840004-11
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840004-11 is: 1795
840004AG-11
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REV.A OCTOBER 3, 2005
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PRELIMINARY
ICS840004-11
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
840004AG-11
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REV.A OCTOBER 3, 2005
9
PRELIMINARY
ICS840004-11
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS840004AG-11
ICS840004AG-11T
ICS840004AG-11LF
ICS840004AG-11LFT
ICS840004A11
ICS840004A11
ICS40004A11L
ICS40004A11L
20 Lead TSSOP
tube
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
20 Lead TSSOP
2500 tape & reel
tube
20 Lead "Lead-Free" TSSOP
20 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
840004AG-11
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REV.A OCTOBER 3, 2005
10
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