ICS501 [ICSI]
LOCO PLL CLOCK MULTIPLIER; LOCO PLL时钟乘法器
| 型号： | ICS501 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOCO PLL CLOCK MULTIPLIER |
| 文件： | 总6页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS501
LOCO™ PLL CLOCK MULTIPLIER
Description
Features
TM
The ICS501 LOCO is the most cost effective way to
generate a high-quality, high-frequency clock output
from a lower frequency crystal or clock input. The name
LOCO stands for Low Cost Oscillator, as it is designed
to replace crystal oscillators in most electronic
systems. Using Phase-Locked Loop (PLL) techniques,
the device uses a standard fundamental mode,
inexpensive crystal to produce output clocks up to 160
MHz.
• Packaged as 8-pin SOIC or die
• Available in Pb (lead) free package
• ICS’ lowest cost PLL clock
• Zero ppm multiplication error
• Input crystal frequency of 5 - 27 MHz
• Input clock frequency of 2 - 50 MHz
• Output clock frequencies up to 160 MHz
• Extremely low jitter of 25 ps (one sigma)
• Compatible with all popular CPUs
• Duty cycle of 45/55 up to 160 MHz
• Nine selectable frequencies
• Operating voltage of 3.3V or 5.5V
• Tri-state output for board level testing
• 25mA drive capability at TTL levels
• Ideal for oscillator replacement
Stored in the chip’s ROM is the ability to generate nine
different multiplication factors, allowing one chip to
output many common frequencies (see table on page
2).
The device also has an output enable pin which
tri-states the clock output when the OE pin is taken low.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined or guaranteed.
For applications which require defined input to output
skew, use the ICS570B.
• Industrial temperature version available
• Advanced, low-power CMOS process
Block Diagram
VDD
2
S1:0
PLL Clock
Multiplier
Circuitry
and ROM
X1/ICLK
CLK
Crystal or
Clock input
Crystal
Oscillator
X2
Optional crystal capacitors
OE
GND
MDS 501 K
1
Revision 071304
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS501
LOCO™PLL Clock Multiplier
Pin Assignment
Clock Output Table
S1 S0
CLK
4X input
Minimum Input
per page 4
20 MHz
0
0
0
M
1
X1/ICLK
VDD
8
7
6
5
1
2
3
4
X2
5.3125X input
5X input
OE
S0
0
per page 4
4 MHz
M
M
M
1
0
6.25X input
2X input
GND
S1
M
1
per page 4
8 MHz
CLK
3.125X input
6X input
0
per page 4
per page 4
per page 4
8 Pin (150 mil) SOIC
1
M
1
3X input
1
8X input
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Common Output Frequency Examples (MHz)
Output
Input
20
24
12
30
10
32
16
33.33
16.66
M, M
37.5
12
40
10
48
12
50
60
10
62.5
20
10
16.66
1, M
Selection (S1, S0) M, M
M, M
1, M
M, M
M, 1
0, 0
0, 0
1, 0
M, 1
Output
64
16
66.66
16.66
0, 0
72
12
75
12
80
10
83.33
16.66
0, 1
90
15
100
20
106.25
20
120
15
125
20
Input
Selection (S1, S0)
0, 0
1, 0
M, 0
1, 1
1, 0
0, 1
0, M
1, 1
M, 0
Pin Descriptions
Pin
Pin
Pin
Type
Pin Description
Number Name
1
2
3
4
5
6
7
8
XI/ICLK
VDD
GND
S1
Input
Power
Power
Crystal connection or clock input.
Connect to +3.3 V or +5 V.
Connect to ground.
Tri-level Iinput
Output
Select 1 for output clock. Connect to GND or VDD or float.
Clock output per table above.
CLK
S0
Tri-level Input
Input
Select 0 for output clock. Connect to GND or VDD or float.
OE
Output enable. Tri-states CLK output when low. Internal pull-up.
Crystal connection. Leave unconnected for clock input.
X2
Output
MDS 501 K
2
Revision 071304
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS501
LOCO™PLL Clock Multiplier
Crystal Load Capacitors
External Components
The total on-chip capacitance is approximately 12 pF. A
parallel resonant, fundamental mode crystal should be
used. The device crystal connections should include
pads for small capacitors from X1 to ground and from
X2 to ground. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS501 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the GND. It must be connected
close to the ICS501 to minimize lead inductance. No
external power supply filtering is required for the
ICS501.
Series Termination Resistor
A 33Ω terminating resistor can be used next to the CLK
pin for trace lengths over one inch.
The value (in pF) of these crystal caps should equal
(C -12 pF)*2. In this equation, C = crystal load
L
L
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 8 pF
[(16-12) x 2] = 8.
MDS 501 K
3
Revision 071304
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS501
LOCO™PLL Clock Multiplier
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS501. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
-40 to +85°C
-65 to +150°C
260°C
Ambient Operating Temperature
Storage Temperature
Soldering Temperature
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
+3.0
+5.5
V
DC Electrical Characteristics
VDD=5.0 V 5% , Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Symbol Conditions
Min.
3.0
Typ.
Max.
Units
Operating Voltage
VDD
5.5
(VDD/2)-1
0.8
V
V
Input High Voltage, ICLK only
Input Low Voltage, ICLK only
Input High Voltage
V
ICLK (pin 1)
ICLK (pin 1)
OE (pin 7)
OE (pin 7)
S0, S1
(VDD/2)+1
IH
V
V
IL
V
2.0
VDD-0.5
2.4
V
IH
Input Low Voltage
V
V
IL
Input High Voltage
V
V
IH
Input Low Voltage
V
S0, S1
0.5
V
IL
Output High Voltage
V
I
I
= -25 mA
= 25 mA
V
OH
OH
OL
Output Low Voltage
V
0.4
V
OL
IDD Operating Supply Current, 20
Short Circuit Current
No load, 100M
CLK output
20
mA
mA
+70
MDS 501 K
4
Revision 071304
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS501
LOCO™PLL Clock Multiplier
Parameter
Symbol Conditions
Pin 7
Min.
Typ.
270
4
Max.
Units
kΩ
On-Chip Pull-up Resistor
Input Capacitance, S1, S0, and OE
Nominal Output Impedance
Pins 4, 6, 7
pF
20
Ω
AC Electrical Characteristics
VDD = 5.0 V 5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency, VDD = 4.5 to 5.5 V
F
5
27
50
MHz
MHz
MHz
MHz
MHz
MHz
ns
IN
IN
F
2
F
F
0°C to +70°C
13
13
13
13
160
140
100
90
OUT
-40°C to +85°C
0°C to +70°C
Output Frequency, VDD = 3.0 to 3.6 V
OUT
-40°C to +85°C
0.8 to 2.0 V, Note 1
2.0 to 8.0 V, Note 1
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
t
1
1
OR
t
ns
OF
t
1.5 V, up to
160 MHz
45
10
49-51
55
%
OD
PLL Bandwidth
kHz
ns
Output Enable Time, OE high to
output on
50
50
Output Disable Time, OE low to
tri-state
ns
ps
ps
Absolute Clock Period Jitter
t
t
Deviation from
mean
+70
25
ja
One Sigma Clock Period Jitter
js
Note 1: Measured with 15 pF load.
MDS 501 K
5
Revision 071304
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS501
LOCO™PLL Clock Multiplier
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
8
Symbol
Min
Max
1.75
0.25
0.51
0.25
5.00
4.00
Min
Max
A
A1
B
C
D
E
e
1.35
0.10
0.33
0.19
4.80
3.80
1.27 BASIC
5.80 6.20
0.25
0.40
0°
.0532
.0040
.013
.0075
.1890
.1497
.0688
.0098
.020
.0098
.1968
.1574
E
H
INDEX
AREA
0.050 BASIC
1
2
H
h
L
.2284
.010
.016
0°
.2440
.020
.050
8°
D
0.50
1.27
8°
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
ICS501M
Marking
ICS501M
ICS501M
ICS501I
ICS501I
501MLF
501MLF
-
Shipping Packaging
Tubes
Package
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
ICS501MT
ICS501MI
Tape and Reel
Tubes
ICS501MIT
Tape and Reel
Tubes
Tape and Reel
Die on uncut, probed wafers
Tested die in waffle pack
ICS501MLF
ICS501MLFT
ICS501-DWF
ICS501-DPK
-
“LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 501 K
6
Revision 071304
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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