ICS514MT [ICSI]
LOCO⑩ PLL Clock Generator; LOCO ™ PLL时钟发生器
| 型号： | ICS514MT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOCO⑩ PLL Clock Generator |
| 文件： | 总4页 (文件大小：46K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS514
LOCO™ PLL Clock Generator
Description
Features
• Packaged as 8 pin SOIC
The ICS514 LOCO™ is the most cost effective
way to generate a high quality, high frequency
clock output from a 14.31818 MHz crystal or
clock input. The name LOCO stands for LOw
Cost Oscillator, as it is designed to replace crystal
oscillators in many electronic systems. Using
Phase-Locked-Loop (PLL) techniques, the device
uses a standard, inexpensive crystal to produce
output clocks up to 66.66 MHz.
• ICS’ lowest cost PLL clock plus reference
• Produces common computer frequencies
• Input crystal frequency typically 14.3182 MHz
• Output clock frequencies up to 66.66 MHz
• Low jitter - 40 ps one sigma
• Compatible with all popular CPUs
• Duty cycle of 45/55
Stored in the chip’s ROM is the ability to generate
5 different output frequencies, allowing one chip
to work in different speed processor systems.
• Custom frequencies available
• Operating voltages of 3.0 to 5.5 V
• Power down mode turns off chip
• 25mA drive capability at TTL levels
• Advanced, low power CMOS process
The device also has a power down mode that turns
off the clock outputs when both select pins are low.
In this mode, the internal PLL is not running.
Block Diagram
VDD GND
2
Output
Buffer
S1, S0
PLL
CLK
Clock
Synthesis
and Control
Circuitry
14.31818 MHz
crystal or clock
X1/ICLK
Crystal
Oscillator
Output
Buffer
REF
X2
Optional crystal capacitors
MDS 514 B
1
Revision 080699
Printed 11/13/00
Integrated Circuit Systems • 525 Race Street • San Jose•CA • 95126 • (408)295-9800tel• (408)295-9818fax
ICS514
LOCO™ PLL Clock Generator
Clock Decoding Table (MHz) with
14.31818MHz Crystal or Clock Input
Pin Assignment
S1
0
S0
0
CLK
Multiplier Accuracy
1
2
3
4
8
7
6
5
X1/ICLK
VDD
X2
S1
Power Down CLK
-
-
0
1
25
33.33
40
1.746
2.328
2.794
3.492
4.656
1 ppm
0.008%
1 ppm
1 ppm
0.008%
M
M
1
0
GND
S0
1
0
50
REF
CLK
1
1
66.66
0 = connect directly to ground.
1 = connect directly to VDD.
M = leave unconnected (floating).
CLK and REF stop low in power down state.
Pin Descriptions
Number
Name
X1/ICLK
VDD
GND
REF
CLK
S0
Type Description
1
2
3
4
5
6
7
8
I
P
Crystal connection to 14.31818 MHz crystal or clock input.
Connect to +3.3V or +5V.
P
Connect to ground.
O
O
T I
T I
O
Reference 14.31818 MHz crystal oscillator buffered clock output.
Clock output per table above.
Select 0 for output clock. Connect to GND or VDD or float. See table above.
Select 1 for output clock. Connect to GND or VDD or float. See table above.
Crystal connection to 14.31818 MHz crystal. Leave unconnected for clock input.
S1
X2
Key: I = Input, TI = Tri-Level Input, O = output, P = power supply connection
Notes: 1. With S1 = S0 = 0, the internal PLL is turned off and the CLK output stops low.
The crystal oscillator and REF output are still active.
2. With a clock input, the phase relationship between the input and output clocks can
change each time the device is powered on. If a fixed phase relationship is required,
please use our ICS571 or other zero delay multipliers.
MDS 514 B
2
Revision 080699
Printed 11/13/00
Integrated Circuit Systems • 525 Race Street • San Jose•CA • 95126 • (408)295-9800tel• (408)295-9818fax
ICS514
LOCO™ PLL Clock Generator
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (stresses be ond these can permanentl damage the device)
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
7
VDD+0.5
VDD+0.5
70
V
V
-0.5
-0.5
0
Clock Output
V
Ambient Operating Temperature
Soldering Temperature
Storage temperature
°C
°C
°C
Max of 10 seconds
260
-65
150
DC CHARACTERISTICS (VDD = 5.0 V unless otherwise noted)
Operating Voltage, VDD
3
5.5
(VDD/2)-1
0.8
V
V
Input High Voltage, VIH, ICLK only
Input Low Voltage, VIL, ICLK only
Input High Voltage, VIH
ICLK (Pin 1)
(VDD/2)+1
VDD/2
VDD/2
ICLK (Pin 1)
V
S0
2
V
Input Low Voltage, VIL
S0
V
Input High Voltage, VIH
S1
VDD-0.5
V
Input Low Voltage, VIM
S1
VDD/2
V
Input Low Voltage, VIL
S1
0.5
0.4
V
Output High Voltage, VOH
Output Low Voltage, VOL
IDD Operating Supply Current
IDD Power Down Supply Current, 3.3 V
Short Circuit Current
IOH=-25mA
IOL=25mA
No Load, 66.66MHz
S1 = S0 = 0
CLK output
Pin 6
2.4
V
V
20
1.5
±70
270
4
mA
mA
mA
k Ω
pF
On-Chip Pull-up Resistor
Input Capacitance, S1, S0
Pins 6, 7
AC CHARACTERISTICS (VDD = 5.0 V unless otherwise noted)
Input Frequency, crystal input
5
14.31818
14.31818
66.66
66.66
1
27
50
MH z
MH z
MH z
MH z
ns
Input Frequency, clock input
2
Output Frequency
VDD = 4.5 to 5.5 V
VDD = 3.0 to 3.6 V
0.8 to 2.0V
14
14
140
100
Output Frequency
Output Clock Rise Time
Output Clock Fall Time
2.0 to 0.8V
1
ns
Output Clock Duty Cycle
1.5V, up to 140 MHz
45
49 to 51
5
55
10
50
%
Power up time, from PD to outputs stable
Power down time, from running to PD state
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
ms
ns
Deviation from mean
±110
40
ps
ps
MDS 514 B
3
Revision 080699
Printed 11/13/00
Integrated Circuit Systems • 525 Race Street • San Jose•CA • 95126 • (408)295-9800tel• (408)295-9818fax
ICS514
LOCO™ PLL Clock Generator
External Components / Crystal Selection
The ICS514 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be
connected close to the ICS514 to minimize lead inductance. No external power supply filtering is required
for this device. A 33Ω terminating resistor can be used next to the CLK and REF pins. The total on-chip
capacitance is approximately 12 pF, so a parallel resonant, fundamental mode crystal should be used. For
crystals with a specified load capacitance greater than 12 pF, crystal capacitors should be connected from
each of the pins X1 and X2 to Ground as shown in the Block Diagram on page 1. The value (in pF) of
these crystal caps should be = (C -12)*2, where C is the crystal load capacitance in pF. These external
L
L
capacitors are only required for applications where the exact frequency is critical. For a clock input,
connect to X1 and leave X2 unconnected (no capacitors on either).
Package Outline and Package Dimensions
8 pin SOIC
E
H
Inches
Millimeters
Min Max
0.055 0.068 1.397 1.7272
Pin 1
Symbol Min
Max
A
b
0.013 0.019 0.330
0.185 0.200 4.699
0.150 0.160 3.810
0.225 0.245 5.715
0.483
5.080
4.064
6.223
D
E
H
e
h x 45°
D
.050 BSC
0.015
0.016 0.035 0.406
0.004 0.01 0.102
1.27 BSC
A
Q
h
0.381
0.889
0.254
c
L
Q
b
L
e
Ordering Information
Part/Order Number
ICS514M
Marking
ICS514M
ICS514M
Package
8 pin SOIC
8 pin SOIC on tape and reel
Temperature
0-70°C
ICS514MT
0-70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
LOCO is a trademark of ICS
MDS 514 B
4
Revision 080699
Printed 11/13/00
Integrated Circuit Systems • 525 Race Street • San Jose•CA • 95126 • (408)295-9800tel• (408)295-9818fax
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