ICS527R-04T [ICSI]
Clock Slicer User Configurable PECL input Zero Delay Buffer; 时钟切片机用户可配置PECL输入零延迟缓冲器
| 型号： | ICS527R-04T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Clock Slicer User Configurable PECL input Zero Delay Buffer |
| 文件： | 总9页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS527-04
Clock Slicer User Configurable PECL input Zero Delay Buffer
Description
Features
The ICS527-04 Clock Slicer is the most flexible way to
generate an output clock from an input clock with zero
skew. The user can easily configure the device to
produce nearly any output clock that is multiplied or
divided from the input clock. The part supports
non-integer multiplications and divisions. Using
Phase-Locked Loop (PLL) techniques, the device
accepts an input clock up to 200 MHz and produces an
output clock up to 160 MHz.
• Packaged as 28-pin SSOP (150 mil body)
• Synchronizes fractional clocks rising edges
• CMOS in to PECL out
• PECL in to PECL out
• Pin selectable dividers
• Zero input to output skew
• User determines the output frequency - no software
needed
• Slices frequency or period
The ICS527-04 aligns rising edges on PECLIN with
FBPECL at a ratio determined by the reference and
feedback dividers.
• Input clock frequency of 1.5 MHz - 200 MHz
• Output clock frequencies up to 160 MHz
• Very low jitter
• Duty cycle of 45/55
• Operating voltage of 3.3 V
For other PECL output clocks, see the ICS507-01,
ICS525-03, or the MK3707. For PECL in and CMOS
out, see the ICS527-02. For CMOS in and PECL out
with zero delay, use the ICS527-03.
• Advanced, low power CMOS process
Block Diagram
R6:R0
7
560 ohm
VDD
VDD
2
VDD
RES
VCO
Divide
by 2
68 ohm
1
0
Reference
Divider
PECLIN
PECLIN
PECLO
PECLO
180 ohm
Phase Comparator,
Charge Pump, and
Loop Filter
Output
Divider
VDD
Divide
by 2
FBPECL
1
0
Feedback
Divider
68 ohm
FBPECL
180 ohm
2
2
GND
7
IRANGE
F6:F0
S1:S0
MDS 527-04 D
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Revision 122804
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS527-04
Clock Slicer User Configurable PECL input Zero Delay Buffer
Pin Assignment
Output Frequency and Output
Divider Table
R 5
1
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
R 4
R 6
2
R 3
S1
Pin 5
S0
Pin 4
Output Frequency (MHz)
PECLO Output Pair
IR A N G E
S 0
3
R 2
4
R 1
S 1
5
0
0
1
1
0
1
0
1
10 - 80
5 - 40
R 0
V D D
6
V D D
P E C L O
P E C L O
G N D
R E S
F 6
F B P E C L
F B P E C L
G N D
7
2.5 - 20
20 -160
8
9
1 0
1 1
1 2
1 3
1 4
P E C L IN
P E C L IN
F 0
IRANGE Setting Table
F 5
F 1
F 4
IRANGE
Criteria
F 2
F 3
0
1
if (FBPECL < 80 MHz) and (PECLIN < 80 MHz)
if (FBPECL > 80 MHz) or (PECLIN > 80 MHz)
28-pin (150 mil) SSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 - 2
24 - 28
R5, R6,
R0-R4
Input
Reference divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up.
3
4 - 5
6, 23
7
IRANGE
S0, S1
VDD
Input
Input
Power
Input
Input
Power
Input
Input
Input
Set for proper frequency range of input clocks. See table above.
Select pins for output frequency range. See table above. Internal pull-up.
Connect to +3.3 V.
FBPECL
FBPECL
GND
PECL feedback input to PLL.
8
PECL feedback input to PLL.
9, 20
10
Connect to ground
PECLIN
PECLIN
F0-F6
PECL input clock.
11
Complementary PECL input clock.
12 - 18
Feedback divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up
19
21
22
RES
BIAS
Resistor connection to VDD for setting level of PECL outputs.
PECLO
PECLO
Output Complementary PECL output.
Output PECL output. Rising edge aligns with PECLIN when connected directly to
FBPECL.
MDS 527-04 D
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Revision 122804
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS527-04
Clock Slicer User Configurable PECL input Zero Delay Buffer
External Components
Decoupling Capacitors
Determining ICS527-04 Divider Settings
The ICS527-04 requires two 0.01µF decoupling
capacitors to be connected between VDD and GND,
one on each side of the chip. They must be connected
close to the device to minimize lead inductance. The
output levels can be adjusted for different output and
load impedances. Refer to application note MAN09 for
more information on the RES and resistor network
values for the output clocks.
The user has full control in setting the desired output
clock over the range shown in the table on page 2. The
user should connect the divider select input pins
directly to ground (or VDD, although this is not required
because of internal pull-ups) during Printed Circuit
Board layout, so that the ICS527-04 automatically
produces the correct clock when all components are
soldered. It is also possible to connect the inputs to
parallel I/O ports in order to switch frequencies. The
configuration inputs: IRANGE, S1, S0, R6...0, F6...0
are compatible with CMOS or TTL levels.
PECL Termination Networks
The PECLO to FBPECL and PECLO to FBPECL
connections should be made directly underneath the
device, unless feedback is being routed through other
devices. The resistor divider networks should be placed
as close to the outputs as possible.
The output of the ICS527-04 can be determined by the
following simple equation:
FDW + 2
RDW + 2
-----------------------
FB Frequency = Input Frequency ×
Typical 50 Ω termination is shown in the Block Diagram
on page 1. For other termination schemes, see
MAN09.pdf.
Where:
Reference Divider Word (RDW) = 0 to 127
Feedback Divider Word (FDW) = 0 to 127
FB Frequency is the same as the output
frequency
Eliminating the Delay Through Buffers or
Other Components
More complicated feedback schemes can be used,
such as incorporating low skew, multiple output buffers
in the feedback path. An example of this is given later in
the datasheet. The fundamental property of the
Additionally, the following operating ranges should be
observed:
ICS527-04 is that it aligns rising edges on CLKIN and
FBPECL at a ratio determined by the reference and
feedback dividers. This means that any delay in the
feedback path will cause the PECL output edge to lead
PECLIN by the delay amount. So, by taking the PECL
output from another device as the input to FBPECL, the
delay through the other device can be eliminated.
Input Frequency
------------------------------------------
300kHz <
RDW + 2
S1 and S0 should be selected depending on the
output frequency. The table on page 2 gives the
ranges.
The dividers are expressed as integers. For example, if
a 50 MHz output on CLK1 is desired from a 40 MHz
input, the reference divider word (RDW) should be 2
and the feedback divider word (FDW) should be 3
which gives the required 5/4 multiplication. If multiple
choices of dividers are available, then the lowest
numbers should be used. In this example, the output
divide (OD) should be selected to be 2. Then R6:R0 is
0000010, F6:F0 is 0000011 and S1:S0 is 00.
Setting the Clock Slicer
Use IRANGE to select the input frequency range. If
either the PECLIN or FBPECL pair frequencies are
greater than (or equal to) 80 MHz, connect IRANGE to
VDD, or let it float. If both frequencies are less than 80
MHz, connect IRANGE to ground.
Choose S1 and S0 from the table on page 2,
depending on the output frequency.
If you need assistance determining the optimum divider
settings, please send an e-mail to ics-mk@icst.com
with the desired input clock and the desired output
frequency.
Finally, the divider settings should be selected.
Following is a description of how the dividers should be
set.
MDS 527-04 D
3
Revision 122804
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS527-04
Clock Slicer User Configurable PECL input Zero Delay Buffer
Typical Example
The following connection diagram shows the implementation of the example from the previous section.
This will generate a 50 MHz clock synchronously with a 40 MHz input. The layout diagram below will
produce the waveforms shown on the bottom of the example.
VDD
R5
R4
R3
R6
IRANGE
S0
R2
R1
0.01 F
VDD
S1
R0
0.01 F
VDD
FBPECL
FBPECL
VDD
PECL
PECL
GND
RES
F6
50 MHz
180
GND
PECLIN
PECLIN
F0
40 MHz
40 MHz
PECL output resistor network (50 ohm) is not
shown, but is identical to PECL
560
F5
F1
F4
F2
F3
40 MHz
(PECLIN shown)
50 MHz PECL
50 MHz PECL
MDS 527-04 D
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Revision 122804
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS527-04
Clock Slicer User Configurable PECL input Zero Delay Buffer
Multiple Output Example
In this example, an input clock of 125 MHz is used. Four low skew copies of 50 MHz PECL are required
aligned to the 125 MHz input clock. The following solution uses the ICS554-01A, which is a 1 to 4 PECL
buffer with low pin to pin skew.
VDD
NC
OE
R5
R4
R3
R6
IRANGE
S0
R2
VDD
Q0
VDD
Q3
R1
0.01 F
RN
RN
S1
R0
0.01 F
VDD
FBPECL
FBPECL
VDD
PECLO
PECLO
GND
RES
F6
Q0
Q3
RN
RN
RN
RN
50 MHz
0.01 F
0.01 F
RN
RN
RN
GND
PECLIN
PECLIN
F0
Q2
Q1
125 MHz
125 MHz
560
RN
Q1
Q2
F5
F1
F4
GND
IN
GND
IN
F2
F3
The layout design above produces the waveforms shown below.
125 MHz, PECLIN
50 MHz, PECLO
(Complementary outputs are not shown)
Using the equation for selecting dividers gives:
(FDW + 2)
50 MHz = 125 MHz *
(RDW + 2)
If FDW = 0, then RDW = 3. This gives the required divide-by-5 function. Setting pin IRANGE = 1 (by leaving
it unconnected and using the internal pull-up) allows a higher speed input clock like the 125 MHz. The
FBPECL pair pins are connected to the Q1 outputs (chosen arbitrarily) of the ICS554. This aligns all the
outputs of the ICS554 with the 125 MHz input since the ICS527-04 aligns rising edges on the PECLIN and
FBPECL pins.
RN
In this example, the resistor network needed for each PECLO output is represented by the
boxes.
MDS 527-04 D
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Revision 122804
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS527-04
Clock Slicer User Configurable PECL input Zero Delay Buffer
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via.
2) PECL termination networks should be located as
close to the outputs as possible.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No via’s should be used
between decoupling capacitor and VDD pin. The PCB
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS527-04. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70°C
-65 to +150°C
125°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
+3.15
+3.3
+3.45
V
MDS 527-04 D
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Revision 122804
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS527-04
Clock Slicer User Configurable PECL input Zero Delay Buffer
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70°C
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Symbol
Conditions
Min.
3.15
2
Typ.
Max.
Units
VDD
3.3
3.45
V
V
V
V
V
IH
V
0.8
1
IL
Peak to Peak Input
Voltage
Pins 7, 8, 10, 11
Pins 7, 8, 10, 11
0.3
Common Mode Range
Output High Voltage
Output Low Voltage
VDD-1.4
2.4
VDD-0.6
0.4
V
V
V
I
I
= -12 mA
= 12 mA
OH
OH
OL
V
V
OL
Operating Supply
Current
IDD
15 MHz in, 60 MHz
out, no load
8
mA
Input Capacitance
C
4
pF
IN
On-chip pull-up resistor
R
configuration inputs
270
kΩ
PU
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70° C
Parameter
Symbol
Conditions
Min.
1.5
4
Typ. Max. Units
Input Frequency
F
200
160
55
MHz
MHz
%
IN
Output Frequency, CLK1
Output Duty Cycle
F
0 to +70°C
OUT
t
45
50
90
40
OD
Absolute Clock Period Jitter
One sigma Clock Period Jitter
t
Deviation from mean
ps
ja
t
ps
js
PECLIN to PECLO,
Note 1
Input to output skew
Device to device skew
t
-250
250
500
ps
ps
IO
Common CLKIN,
measured at FBPECL
t
pi
Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
100
80
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
67
Thermal Resistance Junction to Case
60
MDS 527-04 D
7
Revision 122804
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS527-04
Clock Slicer User Configurable PECL input Zero Delay Buffer
Marking Diagram
28
15
$$###-###
YYWW
ICS527R-04
ICS
1
14
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
MDS 527-04 D
8
Revision 122804
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS527-04
Clock Slicer User Configurable PECL input Zero Delay Buffer
Package Outline and Package Dimensions (28-pin SSOP, 150 mil Body, 0.025 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Millimeters
Inches
Min
28
Symbol
Min
Max
1.75
0.25
1.50
0.30
0.25
10.00
6.20
4.00
Max
.069
.010
.059
.012
.010
.394
.244
.157
A
A1
A2
b
1.35
0.10
--
0.20
0.18
9.80
5.80
3.80
.053
.0040
--
.008
.007
.386
.228
.150
E1
E
INDEX
AREA
C
D
E
1
2
E1
e
L
0.635 Basic
0.025 Basic
D
0.40
0°
1.27
.016
.050
8°
α
8°
0°
aaa
--
0.10
--
0.004
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa C
Ordering Information
Shipping
packaging
Part / Order Number
Marking
Package
Temperature
ICS527R-04
ICS527R-04
ICS527R-04
Tubes
28-pin SSOP
28-pin SSOP
0 to +70°C
0 to +70°C
ICS527R-04T
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments
MDS 527-04 D
9
Revision 122804
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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