ICS5314AI11L [ICSI]
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER; 低偏移， 1到5差分至2.5V / 3.3V LVPECL扇出缓冲器
| 型号： | ICS5314AI11L |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER |
| 文件： | 总18页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS85314I-11 is a low skew, high perfor- • 5 differential 2.5V/3.3V LVPECL outputs
ICS
HiPerClockS™
mance 1-to-5 Differential-to-2.5V/3.3V LVPECL
• Selectable differential CLKx, nCLKx inputs
fanout buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS85314I-11 has two selectable dif-
• CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the
following differential input levels: LVPECL, LVDS, LVHSTL,
HCSL, SSTL
ferential clock inputs. The CLK0, nCLK0 and CLK1, nCLK1
pairs can accept most standard differential input levels. The
clock enable is internally synchronized to eliminate runt clock
pulses on the outputs during asynchronous assertion/
deassertion of the clock enable pin.
• Maximum output frequency: 700MHz
• Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
Guaranteed output and part-to-part skew characteristics make
the ICS85314I-11 ideal for those applications demanding well
defined performance and repeatability.
• Output skew: 30ps (maximum)
• Part-to-part skew: 350ps (maximum)
• Propagation delay: 1.8ns (maximum)
• RMS phase jitter @ 155.52MHz (12kHz - 20MHz):
0.05ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
nCLK_EN
VCC
nCLK1
CLK1
RESERVED
nCLK0
CLK0
D
nCLK_EN
Q
CK
CLK0
nCLK0
0
Q0
nQ0
CLK1
nCLK1
1
Q1
nQ1
CLK_SEL
VEE
CLK_SEL
nQ4
Q2
nQ2
ICS85314I-11
20-LeadTSSOP
Q3
nQ3
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Q4
nQ4
TopView
ICS85314I-11
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm Package Body
M Package
TopView
85314AGI-11
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REV.C MAY 24, 2005
1
ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
VEE
Type
Description
Output
Output
Output
Output
Output
Power
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
3, 4
5, 6
7, 8
9, 10
11
Negative supply pin.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs.
12
CLK_SEL
Input
Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVTTL / LVCMOS interface levels.
13
14
CLK0
nCLK0
RESERVED
CLK1
Input
Input
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
Do not connect.
15
16
Input
Input
Pulldown Non-inverting differential clock input.
17
nCLK1
VCC
Pullup
Inverting differential clock input.
18, 20
Power
Positive supply pins.
Synchronizing clock enable. When LOW, clock outputs follow clock
19
nCLK_EN
Input
Pulldown input. When HIGH, Q outputs are forced low, nQ outputs are forced
high. LVTTL / LVCMOS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
51
51
kΩ
kΩ
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ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
nCLK_EN
CLK_SEL
Selected Source
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
CLK1, nCLK1
Q0:Q4
Enabled
nQ0:nQ4
Enabled
0
0
1
1
0
1
0
1
Enabled
Enabled
Disabled; LOW
Disabled; LOW
Disabled; HIGH
Disabled; HIGH
After nCLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1, nCLK1 inputs
as described in Table 3B.
Enabled
Disabled
nCLK0, nCLK1
CLK0, CLK1
nCLK_EN
nQ0:nQ4
Q0:Q4
FIGURE 1. nCLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK0 or CLK1 nCLK0 or nCLK1
Q0:Q4
LOW
nQ0:nQ4
HIGH
0
1
1
0
Differential to Differential
Differential to Differential
Non Inverting
Non Inverting
HIGH
LOW
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ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
CC
Inputs, V
-0.5V to VCC + 0.5 V
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
73.2°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Power Supply Voltage
Power Supply Current
2.375
3.3
3.8
80
V
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage nCLK_EN, CLK_SEL
2
VCC + 0.3
0.8
V
V
Input Low Voltage nCLK_EN, CLK_SEL
Input High Current CLK_SEL, nCLK_EN
Input Low Current CLK_SEL, nCLK_EN
-0.3
VIN = VCC = 3.8V
150
µA
µA
IIL
VCC = 3.8V, VIN = 0V
-5
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
V
CC = VIN = 3.8V
CC = VIN = 3.8V
150
150
µA
µA
µA
µA
V
IIH
Input High Current
V
V
CC = 3.8V, VIN = 0V
CC = 3.8V, VIN = 0V
-150
-5
IIL
Input Low Current
V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
V
CC - 0.85
V
NOTE 1: For single ended applications the maximum input voltage for CLKx, nCLKx is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.6
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum
Units
fMAX
Output Frequency
700
MHz
Propagation Delay, Low to High;
NOTE 1
tpLH
IJ 700MHz
1.0
1.4
1.8
30
ns
ps
ps
tsk(o)
tjit (Ø)
Output Skew; NOTE 2, 5
RMS Phase Jitter (Random);
NOTE 4
Integration Range:
(12kHz - 20MHz)
0.05
tsk(pp)
tS
Part-to-Part Skew; NOTE 3, 5
Setup Time
350
ps
ps
ps
ps
ps
nCLK_EN to CLK
nCLK_EN to CLK
20% to 80%
50
50
tH
Hold Time
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
45
700
55
IJ 700MHz
All parameters measured at fMAX unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: Please refer to Phase Noise Plot.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TYPICAL PHASE NOISE AT 155.52MHZ
0
-10
-20
155.52MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.05ps (typical)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
Raw Phase Noise Data
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nCLK0,
nCLK1
LVPECL
VEE
VPP
VCMR
Cross Points
nQx
CLK0,
CLK1
-1.8V -0.375V
VEE
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
nCLK0,
nCLK1
CLK0,
CLK1
nQ0:nQ4
nQy
Q0:Q4
Qy
tPD
tsk(o)
OUTPUT SKEW
PROPAGATION DELAY
nQ0:nQ4
80%
tF
80%
Q0:Q4
VSWING
20%
tPW
Clock
20%
tPERIOD
Outputs
tR
tPW
tPERIOD
odc =
x 100%
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin. The
ratio of R1 and R2 might need to be adjusted to position the
V_REF in the center of the input voltage swing. For example, if
the input clock swing is only 2.5V andVCC = 3.3V, V_REF should
be 1.25V and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK INPUT:
LVPECL OUTPUT
For applications not requiring the use of a clock input, it can All unused LVPECL outputs can be left floating. We
be left floating. Though not required, but for additional recommend that there is no trace attached. Both sides of the
protection, a 1kΩ resistor can be tied from the CLK input to differential output pair should either be left floating or
ground.
terminated.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, faces suggested here are examples only. Please consult with
HCSL and other differential signals. Both VSWING and VOH must the vendor of the driver component to confirm the driver termi-
meet the VPP and VCMR input requirements. Figures 3A to 3E nation requirements. For example in Figure 3A, the input ter-
show interface examples for the HiPerClockS CLK/nCLK in- mination applies for ICS HiPerClockS LVHSTL drivers. If you
put driven by the most common driver types. The input inter- are using an LVHSTL driver from another vendor, use their
termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
designed to drive 50Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 4A and
4B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUTTERMINATION
FIGURE 4B. LVPECL OUTPUTTERMINATION
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ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for close to ground level. The R3 in Figure 5B can be eliminated
2.5V LVPECL driver.These terminations are equivalent to ter- and the termination is shown in Figure 5C.
minating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driver
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 5A. 2.5V LVPECL DRIVERTERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVERTERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 5C. 2.5V LVPECLTERMINATION EXAMPLE
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ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85314I-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85314I-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 80mA = 304mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power_MAX (3.465V, with all outputs switching) = 304mW + 151mW = 455mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W perTable 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.455W * 66.6°C/W = 115°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 6B. THERMAL RESISTANCE θJA FOR 20-PIN SOIC, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
65.7°C/W
39.7°C/W
500
57.5°C/W
36.8°C/W
Single-Layer PCB, JEDEC StandardTest Boards
Multi-Layer PCB, JEDEC StandardTest Boards
83.2°C/W
46.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 1.0V
OH_MAX
CC_MAX
)
= 1.0V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
85314AGI-11
www.icst.com/products/hiperclocks.html
REV.C MAY 24, 2005
13
ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θ byVelocity (Linear Feet per Minute)
JA
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 7B. θJAVS. AIR FLOW TABLE FOR 20 LEAD SOIC
θ byVelocity (Linear Feet per Minute)
JA
0
200
65.7°C/W
39.7°C/W
500
57.5°C/W
36.8°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
46.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85314I-11 is: 674
Compatible to part number MC100LVEP14
85314AGI-11
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REV.C MAY 24, 2005
14
ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8A. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum Maximum
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
85314AGI-11
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REV.C MAY 24, 2005
15
ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - M SUFFIX FOR 20 LEAD TSSOP
TABLE 8B. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
20
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
12.60
7.40
2.55
0.51
0.32
13.00
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119
85314AGI-11
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REV.C MAY 24, 2005
16
ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
20 lead TSSOP
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS85314AGI-11
ICS85314AGI-11T
ICS85314AGI-11LF
ICS85314AGI-11LFT
ICS85314AMI-11
ICS85314AI11
ICS85314AI11
ICS5314AI11L
ICS5314AI11L
ICS85314AI-11
ICS85314AI-11
20 lead TSSOP
2500 tape & reel
tube
20 lead "Lead-Free" TSSOP
20 lead "Lead-Free" TSSOP
20 lead SOIC
2500 tape & reel
tube
ICS85314AMI-11T
20 lead SOIC
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
85314AGI-11
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REV.C MAY 24, 2005
17
ICS85314I-11
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
T1
2
Pin Description Table - Pin 14 & 17, nCLKx, deleted partial description and
added Pullup in Type column.
T2
2
4
7
Pin Characteristics Table - CIN changed 4pF max. to 4pF typical.
AMR - corrected Output rating.
A
6/11/03
Added Wiring the Differential Input to Accept Single Ended Levels section.
8
1
5
Added Differential Clock Input Interface section.
Added Phase Noise bullet in Features section.
AC Characteristics Table - added RMS Phase Jitter.
Added Phase Jitter Plot.
T5
B
6
8/11/04
8
9
1
Updated Termination for 3.3V LVPECL Output diagrams.
Added Termination for 2.5V LVPECL Output section.
Features section - added Lead-Free bullet.
T1
T9
2
16
Pin Description Table - corrected CLK_SEL description.
Ordering Information Table - added "Lead-Free" part number for TSSOP
package.
B
C
D
3/22/05
5/24/05
9/23/05
1
5
Features section - changed Part-to-Part Skew from 250ps max. to 350ps max.
T5
AC Characteristics table - changed Part-to-Part Skew from 250ps max. to
350ps max.
LVPECL DC Characteristics Table - changed VOH max from VCC - 1.0V to
VCC - 0.9V.
T4D
5
8
Application Information Section - added Recommendations for Unused Input
and Output Pins.
85314AGI-11
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REV.C MAY 24, 2005
18
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