ICS5342-1 [ICSI]
Analog IC ; 模拟IC\n
| 型号： | ICS5342-1 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Analog IC
|
| 文件： | 总36页 (文件大小：1013K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS5342
GENDAC
16-Bit Integrated Clock-LUT-DAC
General Description
Features
The ICS5342 GENDAC is a combination of dual programma-
ble clock generators, a 256 x 18-bit RAM, and a triple 8-bit
video DAC. The GENDAC supports 8-bit pseudo color appli-
cations, as well as 15-bit, 16-bit, and 24-bit True Color bypass
for high speed, direct access to the DACs.
•
•
•
Triple video DAC, dual clock generator, and 16 bit pixel
port
Dynamic mode switch allows switching of color depth
on a pixel by pixel basis
24 (packed and sparse), 16, 15, or 8-bit pseudo color
pixel mode supports True Color, Hi-Color, and VGA
modes
The RAM makes it possible to display 256 colors selected
from a possible 262,144 colors. The dual clock generators use
Phase Locked Loop (PLL) technology to provide program-
mable frequencies for use in the graphics subsystem. The vid-
•
•
High speed 256 x 6 x 3 color palette (135 MHz) with
bypass mode and 8-bit DACs
eo clock contains
8
frequencies, all of which are
Eight programmable video (pixel) clock frequencies
(CLK0)
programmable by the user. The memory clock has two pro-
grammable frequency locations.
•
•
•
•
•
•
•
•
•
•
DAC power down in blanking mode
Anti-sparkle circuitry
The three 8-bit DACs on the ICS5342 are capable of driving
singly or doubly-terminated 75Ω loads to nominal 0 - 0.7
volts at pixel rates up to 135 MHz. Differential and integral
linearity errors are less than 1 LSB over full temperature and
VDD ranges. Monotonicity is guaranteed by design. On-chip
pixel mask register allows displayed colors to be changed in
a single write cycle rather than by modifying the color palette.
On-chip loop filters reduce external components
Standard CPU interface
Single external crystal (typically 14.318 MHz)
Monitor sense
Internal voltage reference
135 MHz (-3), 110 MHz (-2) & 80 MHz (-1) versions
Very low clock jitter
ICS is the world leader in all aspects of frequency (clock) gen-
eration for graphics, using patented techniques to produce
low jitter video timing.
Two latched frequency select pins or three non-latched
frequency select pins (programmable)
•
Hardware video checksum for manufacturing tests
Block Schematic
PCLK
COMPARE
SENSE*
24
BYPS
LATCH
P0-P15
BUFF.
RED
TRIPLE
6/8-BIT
DAC
GREEN
PIXEL
ADR
AND
BLUE
MUX
LATCH
24
COLOR
RSET
VREF
PALETTE
256 x 18
BIT
MASK
18
8
D0-D7
NORM
MICRO-
PROCESSOR
INTERFACE
WR*
16
RD*
TIMING
GEN.
MUX.
PCLK
RS0-RS2
STROBE
CS0-CS2
CTL
2X
MODE
CLK0
BLANK*
16
8 PLL
PARAMETER &
CLK0 PLL
XIN
XTAL
OSC
1 PLL
CLK1
PARAMETER &
CLK1 PLL
XOUT
5342_01.ai
REV. 0.9.0
ICS5342
GENDAC
Pin Configuration
CGND
CLK1
P14
P15
D0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
CGND
PCLK
P7
P6
P5
P4
P3
P2
P1
P0
XVDD
XOUT
XIN
XGND
VREF
N/C
D1
D2
D3
D4
D5
D6
D7
GENDAC II
ICS5342
WR*
RS0
RS1
MSW
CGND
DGND
5342_02
ICS5342 (68-pin PLCC)
Pin Description (68-pin PLCC)
Symbol
Pin #
21-14
Type
I/O
Description
D7 - D0
Systems data bus bidirectional data I/O lines – used by host microprocessor for
internal register read and write operations (using active low RD and WR respec-
tively) for six internal registers: Pixel Address, Color Value, Pixel Mask, PLL
Address, PLL Parameter, and Command
During the write cycle, the rising edge of WR latches the data into the selected
register (set by the status of the three RS pins).
The rising edge of RD determines the end of the read cycle.
The RD set logical high indicates that data I/O lines no longer contain infor-
mation from the selected register and will be tri-stated.
RD
5
Input
Input
Input
RAM/PLL read enable bus control signal – in active low state, any information
present on the internal data bus is available on the Data I/O lines, D0-D7
Active low RAM/PLL write enable bus control signal – controls write timing on
microprocessor interface inputs, D0-D7
Register address select 0 inputs – control selection of one of six internal registers –
inputs are sampled on falling edge of active enable signal (RD or WR)
Crystal input – connect to 14.318 MHz crystal
Crystal output – connect to 14.318 MHz crystal
Mode switch – digital control for selecting primary and secondary pixel color
modes – low selects primary mode – connect to ground if not used
WR
22
RS2-RS0
63,24,23
XIN
XOUT
MSW
48
49
25
Input
Output
Input
2
ICS5342
GENDAC
Pin Description (68-pin PLCC)
Symbol
CLK1
CLK0
Pin #
11
8
Type
Description
Output
Output
Memory clock output – used to time video memory
Video clock output – provides a CMOS level pixel or dot clock frequency to
graphics controller – output frequency is determined by values of PLL registers
Clock select 0 – The status of CS0-1 determines which frequency is selected on
the CLK0 (video) output.
Clock select 1– status of CS0-1 determines which frequency is selected on CLK0
(video) output
Internal reference voltage – normally connects to a 0.1µf capacitor to ground – to
use external Vref, connect 1.235V reference to this pin
Resistor set – pin used to set current level in analog outputs – usually connected
through 1/4W, 1% resistor to ground
Monitor sense – Pin is active low when any of red, green, or blue outputs >385mV.
Sense output is high when all analog outputs are < 275 mV. Chip has on-board
comparators and internal 1.235 V voltage reference. This signal is used to detect
monitor type.
CS0
2
Input
Input
I/O
CS1
3
VREF
RSET
SENSE*
46
42
68
Input
Output
BLUE
GREEN
RED
40
38
37
Output
Output
Output
Color signals from DAC analog outputs – Each DAC comprises several current
sources of which outputs are added together according to the applied binary value.
The outputs are typically used to drive a CRT monitor.
Pixel address lines – Byte-wide information is latched by the rising edge of PCLK
when using the color palette, and is masked by the Pixel Mask register. Values are
used to specify the RAM word address in default mode (accessing RAM). In Hi-
Color XGA, and True Color modes, they represent color data for the DACs.
Ground inputs if they are not used.
P15- P0
13,12,4,1 Input
,
67-64,
58-51
PCLK
59
Input
Pixel Clock – rising edge of PCLK controls latching of the Pixel Address and
BLANK* inputs – clock also controls progress of these values through the three-
stage pipeline of the Color Palette RAM, DAC, and outputs
latches input clock select signals CS0-CS1
Composite BLANK* Signal, active low. When BLANK* is asserted, outputs of
DACs are zero which blacks screen. DACs are automatically powered down to
save current during blanking. Color palette may still be updated through D0-D7
during blanking.
STROBE*
BLANK*
6
7
Input
Input
CVDD
CVDD
AVDD
DVDD
XVDD
CVDD
CGND
CGND
XGND
AGND
DGND
CGND
N/C
9
27
41
43
50
61
10
26
47
36
44
60
28-35,
39,45,
62
-
-
-
-
-
-
-
-
-
-
-
-
-
CLK1 Power Supply – connect to DVDD
CLK0 power supply – connect to AVDD
DAC power supply – Connect to AVDD
Digital power supply
Crystal oscillator power supply– connect to AVDD
CLK power supply – connect to DVDD
VSS for CLK1 – connect to ground.
VSS for CLK0 – connect to ground
VSS for crystal oscillator
DAC ground – connect to ground
Digital ground – connect to ground
VSS for CLK – connect to ground
Not connected – leave floating or tie to ground
3
ICS5342
GENDAC
Internal Registers
RS2
RS1
RS0
Register Name
Description (all registers can be written to and read from)
The GENDAC has a single pixel address register which can be
accessed through either register address 0,0,0 or 0,1,1 – reading
from either register gives the same result.
Writing a value to address 0,0,0:
– specifies an address within the color palette RAM
– initializes the Color Value register
Writing a value to address 0,1,1:
– specifies an address within the color palette RAM
– loads Color Value register with contents of location in
addressed RAM palette and then:
– increments Pixel Address register
0
0
0
1
1
0
1
1
1
Pixel Address
WRITE
Pixel Address
READ
Writing to this 8-bit register is done before writing one or more
color values to color palette RAM.
Writing to this 8-bit register is done before reading one or more
color values from color palette RAM.
The 18-bit Color Value register acts as a buffer between the
microprocessor interface and the color palette. A value may be
read from or written to this register using a three-byte transfer
sequence. The color value is contained in the least significant 6
bits, D0-D5, of the byte read – the most significant 2 bits are set
to zero. The same 6 bits are used when writing a byte. When
reading or writing, data is transferred in the same order – red
byte first, then green, then blue. Each transfer between the Color
Value register and the color palette replaces the normal pixel
mapping operations of the GENDAC for a single pixel.
Color Value
After writing three definitions to this register, its contents are
written to the location in the color palette RAM specified by the
Pixel Address register, before that register increments.
After reading three definitions from this register, the contents of
the location in the color palette RAM specified by the Pixel
Address registers are copied into the Color Value register, and
the Pixel Address register increments.
0
1
0
Pixel Mask
The 8-bit Pixel Mask register can be used to mask selected bits
of the Pixel Address value applied to the Pixel Address inputs
(P7-P0). A one in a position in the mask register leaves the corre-
sponding bit in the Pixel Address unaltered, while a zero sets
that bit to zero. The Pixel Mask register does not affect the Pixel
Address generated by the microprocessor interface when the pal-
ette RAM is being accessed.
1
1
0
1
0
1
PLL Address
WRITE
PLL Address
READ
Writing to this 8-bit register is performed prior to writing one or
more PLL programming values to the PLL Parameter register.
Writing to this 8-bit register is performed prior to reading one or
more PLL programming values from the PLL Parameter register.
4
ICS5342
GENDAC
Internal Registers
RS2
RS1
RS0
Register Name
Description (all registers can be written to and read from)
1
1
1
0
0
1
Command
This 8-bit register selects color mode, for instance 8-bit Pseudo
Color, Hi-Color, True Color, or XGA, and DAC power down.
The registers are reset to pseudo color mode on power up.
PLL Parameter There are 16 PLL parameter registers accessible as indexed by
Read/Write registers. Parameter registers 0F and 0D-00 are two
bytes long and 0E is one byte long. Register 0E is a control reg-
ister. The bits of this register include clock select and enable
functions, the rest contain PLL frequency parameters. After writ-
ing the start index address in the PLL address register, these reg-
isters can be accessed in successive two (or one) bytes. The
address register auto increments after one (0E) or two bytes to
access the entire register
5
ICS5342
GENDAC
Absolute Maximum Ratings
Power Supply Voltage........................................................7 V DC Digital Output Current ......................................... 25 mA
Voltage on any other pin.............. GND 0.5V to VDD + 0.5V Analog Output Current ................................................45 mA
–
Temperature under bias ................................ – 40˚ C to 85˚ C Reference Current......................................................–15 mA
Storage Temperature................................... – 65˚ C to 150˚ C Power Dissipation......................................................... 1.0 W
Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sec-
tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect de-
vice reliability.
Electrical Characteristics
DC CHARACTERISTICS (note: J)
Parameter
Positive supply voltage
Input logic “1” voltage
Input logic “0” voltage
Reference current
Symbol
Min.
4.75
Max.
5.25
Units
Test Conditions
V
V
V
V
DD
IH
V
V
2.0
V
+0.5
DD
– 0.5
–7.0
1.10
0.8
IL
I
–10
1.35
± 10
± 50
250
mA
V
REF
Reference voltage
V
REF
Digital input current
I
I
I
µA
µA
mA
V
V
=max, V ≥V ≥GND
DD IN
IN
DD
Off-state digital output current
Average power supply current
= max, V ≥V ≥GND
DD IN
OZ
DD
DD
I = max, Digital outputs
O
unloaded
DACs in power down mode
Sense logic “1”
I
50
mA
V
no palette access
DACOFF
V
V
V
V
V
V
2.4
2.4
2.4
I = -0.4mA
O
OHS
OLS
OHC
OLC
OH
Sense logic “0”
0.4
0.4
V
I = 0.4mA
O
Clock logic “1”
V
I = -12.0mA
O
Clock logic “0”
V
I = 12.0mA
O
Logic “1”
V
I = -3.2mA, note K
O
Logic “0”
0.4
15
V
I = 3.2mA, note K
OL
O
XIN input clock rise time
XIN input clock fall time
XCLK
XCLK
FD
ns
ns
%
TTL levels
r*
15
TTL levels
f*
Frequency change of CLK0 and
CLK1 over supply and tempera-
ture
0.05
with respect to typical frequency
6
ICS5342
GENDAC
DAC Characteristics
Parameter
Maximum output voltage
Maximum output current
Symbol
V (max)
Min
Max
1.5
Units
Test Conditions
I ≤ 10 mA
V
o
o
I (max)
21
mA
V ≤ 1V
o
o
Full scale error
± 5
±2
±0.5
±1
28
20
6
200
%
%
LSB
LSB
ns
ns
ns
pV.s
note A, B
note B
note B
note B
note C
note C
note C
note C
DAC to DAC correlation
Integral Linearity, 6-bit
Integral Linearity, 8-bit
Full scale settling time*, 6-bit
Full scale settling time*, 8-bit
Rise time (10% to 90%)*
Glitch energy*
PLL AC Characteristics
Parameter
Symbol
f0
Min
Max
Units
Test Conditions
Clock 0 operating range
Clock 1 operating range
25
25
135
135
MHz
MHz
f
1
Output clocks rise time*
Output clocks fall time*
Duty Cycle*
t
t
3
ns
25 pF load, TTL levels
25 pF load, TTL levels
r
r
3
ns
d
40/60
60/40
130 ps
300 ps
25
%
t
Jitter, one sigma*
j
j
ps
1s
abs
Jitter, absolute*
-300 ps
5
ps
Input reference frequency*
f
MHz
Typically 14.318 MHz
ref
* Characterized values only
AC Electrical Characteristics (note: J)
Test
80 MHZ
110MHz
Min Max
9.09
135Mhz
Parameter
PCLK period
Symbol
Units
Conditions
Min
12.5
Max
Min
7.4
Max
t
ns
%
ns
ns
ns
ns
ns
ns
ns
CHCH
PCLK jitter
∆t
*
±2.5
+2.5
note D
CHCH
PCLK width low
PCLK width high
Pixel word setup time
Pixel word hold time
BLANK* setup time
BLANK* hold time
t
t
t
t
t
t
t
5
5
3
3
3
3
3.6
3.6
3
3
3
2
1
2
1
CLCH
CHCL
PVCH
CHPX
BVCH
CHBX
note E
note E
note E
note E
note F
2
3
2
PCLK to valid DAC
output
*
20
20
20
CHAV
7
ICS5342
GENDAC
AC Electrical Characteristics (note: J)
Test
80 MHZ
110MHz
Min Max
135Mhz
Min Max
Parameter
Symbol
Units
Conditions
Min
Max
Differential output
delay
∆t
2
2
2
ns
note G
CHAV
WR* pulse width low
t
t
t
50
50
50
10
50
50
10
ns
ns
ns
WLWH
RLRH
SVWL
RD* pulse width low
50
10
Register select setup
time
write cycle
read cycle
write cycle
read cycle
Register select setup
time
Register select hold
time
Register select hold
time
t
t
t
10
10
10
10
10
10
10
10
10
ns
ns
ns
SVRL
WLSX
RLSX
WR* data setup time
t
t
t
t
t
t
t
10
10
5
10
10
5
10
10
5
ns
DVWH
WHDX
RLQX
RLQV
RHQX
RHQZ
WHWL1
WR* data hold time
Output turn-on delay
RD* enable access time
Output hold time
ns
ns
40
20
40
20
40
20
ns
3
4
3
4
3
4
ns
Output turn-off delay
ns
note H
note I
Successive write inter-
val
cycle
(t
)
)
(t
)
)
)
)
)
)
)
)
)
(t
)
)
)
)
)
CHCH
CHCH
CHCH
CHCH
CHCH
CHCH
CHCH
CHCH
CHCH
CHCH
CHCH
CHCH
CHCH
CHCH
CHCH
WR* followed by read
interval
t
t
t
t
t
t
t
t
4
4
(t
4
(t
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
note I
note I
note I
note I
note I
note I
note I
note I
WHRL1
RHRL1
RHWL1
WHWL2
WHRL2
RHRL2
RHWL2
WHRL3
SOD
(t
CHCH
Successive read interval
4
4
(t
4
(t
(t
CHCH)
CHCH)
CHCH)
RD* followed by write
interval
4
(t
4
(t
4
(t
WR* after color write
RD* after color write
RD* after color read
WR* after color read
4
(t
4
(t
4
(t
4
4
(t
4
(t
)
)
)
(t
CHCH
CHCH
CHCH
CHCH)
CHCH)
8
(t
8
(t
8
(t
8
(t
8
(t
8
(t
)
)
CHCH
RD* after read address
write
8
8
(t
8
(t
(t
CHCH)
CHCH
SENSE* output delay
t
t
1
1
1
µs
XIN input clock rise
time
*
15
15
15
ns
TTL levels
XCLKR
8
ICS5342
GENDAC
AC Electrical Characteristics (note: J)
Test
80 MHZ
110MHz
Min Max
15
135Mhz
Min Max
15
Parameter
Symbol
Units
ns
Conditions
Min
Max
XIN input clock fall
time
t
*
15
TTL levels
XCLKF
* Characterized values only
Notes:
Input rise and fall times (10% to 90%) ............................ 3 ns
Digital input timing reference level ...............................1.5 V
Digital output timing reference level .............0.8 V and 2.4 V
A. Full scale error is derived from design equation:
{[(F.S.I )R – 2.1(I )R ] / [2.1(I )R ]} 100%
OUT
L
REF
L
REF
L
V
= 0 V
= Actual full scale measured output
BLACK LEVEL
Capacitance
1
F.S.I
OUT
C Digital input............................................................... 7 pF
B. R= 37.5 Ω, I
= – 8.88 mA
REF
C Digital output............................................................. 7pF
0
C. Z = 37.5 Ω + 30 pF, I
= – 8.88 mA
C
Analog output ........................................................ 10 pF
I
REF
0A
D. This parameter is the allowed Pixel Clock frequency
variation. It does not permit the Pixel Clock period to
vary outside the minimum values for Pixel Clock
1.4V
(t
) period.
CHCH
CLK
200 Ω
E. The color palette’s pixel address is required to be a valid
logic level with the appropriate setup and hold times at
each rising edge of PCLK (this requirement includes the
blanking period).
25 pF
5342_03
F. The output delay is measured from the 50% point of the
rising edge of CLOCK to the valid analog output. A
valid analog output is defined when the analog signal is
halfway between its successive values.
Clock Load
General Operation
G. This applies to different analog outputs on the same
device.
The ICS5342 GENDAC is intended for use as the analog out-
put stage of raster scan video systems. It contains a high-
speed Random Access Memory of 256 x 18-bit words, three
6/8-bit high-speed DACs, a microprocessor/graphic control-
ler interface, a pixel word mask, on-chip comparators, and
two user programmable frequency generators.
An externally generated BLANK* signal can be applied to
pin 7 of the ICS5342. This signal acts on all three of the ana-
log outputs. The BLANK* signal is delayed internally so that
it appears with the correct relationship to the pixel bit stream
at the analog outputs.
H. Measured at ± 200 mV from steady state output voltage.
I. This parameter allows synchronization between opera-
tions on the microprocessor interface and the pixel
stream being processed by the color palette.
J. The following specifications apply for V = +5V±
DD
0.5V, GND=0. Operating Temperature = 0˚C to 70˚C.
K. Except for SENSE pin.
AC Test Conditions
A pixel word mask is included to allow the incoming pixel
address to be masked. This permits rapid changes to the effec-
Input pulse levels...................................................V to 3V
DD
9
ICS5342
GENDAC
tive contents of the color palette RAM to facilitate such oper- DAC Outputs
ations as animation and flashing objects. Operations on the The outputs of the DACs are designed to be capable of pro-
contents of the mask register can also be totally asynchronous ducing 0.7 V peak white amplitude with an I
of 8.88 mA
REF
to the pixel stream.
when driving a doubly-terminated 75 Ω load. This corre-
) of 37.5
The ICS5342 also includes dual PLL frequency generators sponds to an effective DAC output load (R
EFFECTIVE
providing a video clock (CLK0) and a memory clock (CLK1), Ω. The formula for calculating I
with various peak white
REF
both generated from a single 14.318 MHz crystal. There are voltage/output loading combinations is given below:
eight selectable CLK0 frequencies. All eight are programma-
VPEAKWHITE
ble. There are two selectable and programmable CLK1 fre-
quencies (fA, fB). Default values (Shown in tables: “Video
Clock Default Frequency Registers,” and “Memory Clock
Default Frequency Registers”) are loaded into the appropriate
registers on power up.
IREF = --------------------------------------------
2.1 × REFFECTIVE
Note that for all values of I
and output loading:
REF
V BLACKLEVEL = 0
The reference current I
is determined by the reference
Video Path
REF
voltage V
and the value of the resistor connected to R
REF
SET
The GENDAC supports nine different video modes and is de- pin. V
can be the internal band gap reference voltage or
REF
termined by bits 4-7 of the command register. The default can be overridden by an external voltage. In both cases:
mode is the 8-bit Pseudo Color mode. The other modes are the
bypass 15-bit, 16-bit and 24 bit True Color modes in 8-bit and
16-bit interface, and the 16-bit Pseudo Color (2:1) mode with
2X Clock. The 24-bit True Color has sparse and packed
modes.
IREF = VREF ⁄ RSET
36
38
39
DAC
IREF
VREF
(INT)
IREF
Pseudo Color
8-bit Interface
33
34
RSET
In this mode, Pixel Address, P7-P0 and BLANK* inputs are
sampled on the rising edge of the clock (PCLK) and any
change appears at the analog outputs after three succeeding
rising edges of the PCLK. The DAC output depends on the
data in the color palette RAM.
VREF
REFF
(EXT)
5342_04
DAC Setup
The BLANK* input to the GENDAC acts on all three of the
16-bit Interface
In this mode, Pixel Address, P15-P0 and BLANK* inputs are DAC outputs. When the BLANK* input is low, the DACs are
sampled on the rising edge of the clock (PCLK) and any powered down.
change appears at the analog outputs after three succeeding The connection between the DAC outputs of the ICS5342 and
rising edges of the 2 x ICLK. ICLK frequency is twice the the RGB inputs of the monitor should be regarded as a trans-
PCLK input frequency. The DAC output depends on the data mission line. Impedance changes along the transmission line
in the color palette RAM.
will result in the reflection of part of the video signal back
along the line. These reflections may result in a degradation
of the picture displayed by the monitor.
Bypass Mode
RF techniques should be observed to ensure good fidelity.
The GENDAC supports seven different bypass modes: three The PCB trace connecting the GENDAC to the off-board con-
for byte transfers and four for word transfers. In these modes, nector should be sized to form a transmission line of the cor-
the address pins P0-P15 represent Color Data that is applied rect impedance. Correctly matched RF connectors should be
directly to the DAC. The internal look-up table RAM is ig- used for connection from the PCB to the monitor coaxial cable
nored. During byte transfers, the P8-P15 inputs are”don't and from that cable to the monitor.
care.” Data is always latched on the rising edge of PCLK. There are two recommended methods of DAC termination:
Byte or word framing is internally synchronized with the ris- double termination and buffered signal. Each is described be-
ing edge of BLANK*.
low with its relative merits.
10
ICS5342
GENDAC
Double Termination (Figure 1)
comparators is proportional to the V
(internal or external)
REF
For this termination scheme, a load resistor is placed at both and is typically 0.330 for V =1.235 Volts. The SENSE*
REF
the DAC output and the monitor input. The resistor values pin will be driven low when any analog video output is above
should be equal to the characteristic impedance of the line. 0.385 mV. SENSE* output will be high when all analog out-
Double termination of the DAC output allows both ends of the puts are below 275 mV. This signal is used to detect the type
transmission line between the DAC outputs and the monitor of (or lack of) monitor connected to the system.
inputs to be correctly matched.The result should be an ideal
reflection-free system.
This arrangement is relatively tolerant of variations in trans-
PLL Clock
mission line impedance (e.g. a mismatched connector) since The ICS5342 has dual PLL frequency generators for generat-
no reflections occur from either end of the line. A doubly ter- ing the video clock (CLK0) and memory clock (CLK1) need-
minated DAC output will rise faster than any singly terminat- ed for graphics subsystems. Both of these clocks are
ed output because the rise time of the DAC outputs is generated from a single 14.318 MHz crystal or they can be
dependent on the RC time constant of the load.
driven from an external clock source. The chip includes the
capacitors for the crystal and all of the components needed for
the PLL loop filters, minimizing board component count.
There are eight possible video clock, CLK0, frequencies (f0-
f7) which can be selected by the external pins CS1-CS0. All
clocks are software selectable by setting a bit in the PLL con-
trol register. Frequencies f0-f7 can be programmed for any
frequency by writing appropriate parameter values to the PLL
parameter registers. The default frequencies on power up are
commonly used video frequencies (see table “Video Clock
Default Frequency Registers”). At power up, the frequencies
can be selected by pins CS2-CS0. There are two programma-
ble memory clock frequencies (fA, fB). On power up this fre-
ICS5342
MONITOR
RLOAD
RLOAD
Ground
Ground
5342_05
Double Termination
If the GENDAC drives large capacitive loads (for instance quency defaults to the frequency given in the table:
long cable runs), it may be necessary to buffer the DAC out- “MemoryClock Default Frequency Registers.” The memory
puts. The buffer will have a relatively high input impedance. clock transition between frequencies is smooth and glitch free
The connection between the DAC outputs and the buffer in- if the N2 PLL parameter is not changed from its previous set-
puts should also be considered as a transmission line. The ting.
buffer output will have a relatively low impedance. It should
be matched to the transmission line between it and the monitor
with a series terminating resistor. The transmission line
should be terminated at the monitor.
Video Clock (CLK0) Default Frequency Register *
M & N
Comments
fn
VCLK
(MHz)
Code
f0
25.175
28.322
31.500
36.00
40.00
44.889
7D 50
55 49
2A 43
77 4A
79 49
6F 47
VGA0 (VGA Graphics)
VGA1 (VGA Text)
VESA 640 x 480 @72 Hz
VESA 800 x 600 @56 Hz
VESA 800 x 600 @60 Hz
1024 x 768 @43 Hz Inter-
laced
1024 x 768 @ 60 Hz,
640 x 480 Hi-Color @ 72
Hz
VESA 1024 x 768 @ 70
Hz,
RS
f1
f2
f3
f4
f5
ICS5342
MONITOR
RLOAD
RT
Ground
Ground
f6
f7
65.00
75.00
74 2B
71 29
5342_06
Buffered Signal
SENSE Output
True Color 640 x 480
The GENDAC contains three comparators, one for each of the
DAC output R, G and B lines. The reference voltage to the
* With 14.318 MHz input.
11
ICS5342
GENDAC
Memory Clock (CLK1) Default Frequency Register
Writing new color definitions to a set of consecutive locations
in the RAM is made easy by this auto-incrementing feature.
First, the start address of the set of locations is written to the
write mode Pixel Address register, followed by the color def-
inition of that location. Since the address is incremented after
each color definition is written, the color definition for the
next location can be written immediately. Thus, the color def-
initions for consecutive locations can be written sequentially
to the Color Value register without re-writing to the Pixel Ad-
dress register each time.
MCLK
(MHz)
M & N
Code
fn
fA
Comments
45.00
4F 2B
Memory and GUI sub-
system clock
fB
55.00
79 2E
Memory and GUI sub-
system clock
Microprocessor Interface
Below are listed the six microprocessor interface registers
within the ICS5342, and the register addresses through which
they can be accessed.
Reading from the RAM
To read a color definition, a value specifying the location in
the palette RAM to be read is written to the read mode Pixel
Address register. After this value has been written, the con-
tents of the location specified are copied to the Color Value
register, and the Pixel Address register automatically incre-
ments.
The red, green and blue intensity values can be read by a se-
quence of three reads from the Color Value register. After the
blue value has been read, the location in the RAM currently
specified by the Pixel Address register is copied to the Color
Value register and the Pixel Address again automatically in-
crements. A set of color values in consecutive locations can be
read simply by writing the start address of the set to the read
mode Pixel Address register and then sequentially reading the
color values for each location in the set. Whenever the Pixel
Address register is updated, any unfinished color definition
read or write is aborted and a new one may begin.
Microprocessor Interface Registers
RS2 RS1 RS0
Register Name
0
0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
1
0
Pixel Address (write mode)
Pixel Address (read mode)
Color Value
Pixel Mask
PLL Address (write mode)
PLL Parameter
0
1
0
1
0
1
1
Command
PLL Address (read mode)
Command Register accessed by
(hidden) flag after special
sequence of events.
0/HF
Asynchronous Access to Microprocessor Interface
Accesses to all registers may occur without reference to the
high speed timing of the pixel bit stream being processed by
The Pixel Mask Register
the GENDAC. Data transfers between the color palette RAM The pixel address used to access the RAM through the pixel
and the Color Value register, as well as modifications to the interface is the result of the bitwise AND-ing of the incoming
Pixel Mask register, are synchronized to the Pixel Clock by pixel address and of the contents of the Pixel Mask register.
internal logic. This is done in the period between micropro- This pixel masking process can be used to alter the displayed
cessor interface accesses. Thus, various minimum periods are colors without altering the video memory or the RAM con-
specified between microprocessor interface accesses to allow tents. By partitioning the color definitions by one or more bits
the appropriate transfers or modifications to take place. Ac- in the pixel address, such effects as rapid animation, overlays,
cess to PLL address, PLL parameter and to the command reg- and flashing objects can be produced.
ister are asynchronous to the pixel clock.
The Pixel Mask register is independent of the Pixel Address
The contents of the palette RAM can be accessed via the Col- and Color Value registers.
or Value register and the Pixel Address registers.
The Command Register
Writing to the color palette RAM
The Command register is used to select the various GENDAC
To set a new color definition, a value specifying a location in color modes and to set the power down mode. On power up
the color palette RAM is first written to the Write mode Pixel this register defaults to an 8-bit Pseudo Color mode. This reg-
Address register. The values for the red, green and blue inten- ister can be accessed by control pins RS2-RS0, or by a special
sities are then written in succession to the Color Value regis- sequence of events for graphics subsystems that do not have
ter. After the blue data is written to the Color Value register, the control signal RS2. For graphic systems that do not have
the new color definition is transferred to the RAM, and the RS2, this pin is tied low and an internal flag (HF: Hidden
Pixel Address register is automatically incremented.
Flag) is set when the pixel mask register is read four times
12
ICS5342
GENDAC
consecutively. Once the flag is set, the following Read or ically incremented. For the one byte “0E” register the address
Write to the pixel mask register is directed to the command location is incremented after the first byte write. If this fre-
register. The flag is reset for read or write to any register other quency is selected while programming, the output frequency
than the Pixel Mask register. The sequence has to be repeated will change at the end of the second write.
for any subsequent access to the command register.
Reading the PLL parameter register
The PLL Parameter Register
To read one of the registers of the PLL parameter register the
The CLK0 and CLK1 of the ICS5342 can be programmed for address value corresponding to the location is first written to
different frequencies by writing different values to the PLL the PLL address register. The next PLL parameter read will be
parameter register bank. There are eight registers in the pa- directed to the first byte of the address location pointed by this
rameter register; seven are two bytes long and one (0E) is one index register. A next read of the parameter register will auto-
byte long.
matically be the second byte of this register. At the end of the
second read, the address location is automatically increment-
ed. The address register (0E) is incremented after the first byte
Writing to the PLL parameter register
To write the PLL parameter data, the corresponding address read.
location is first written to the PLL address register. For soft-
ware compatibility with other chips, two address registers are
defined: the write mode PLL address register and the read
mode PLL address register. These are actually a single Read/
Write register in the ICS5342. The next PLL parameter write
will be directed to the first byte of the address location speci-
fied by the PLL address register. The next write to the param-
eter register will automatically be to the second byte of this
register. At the end of the second write the address is automat-
13
ICS5342
GENDAC
Bit 7-4
Color Mode Select - These three bits select the
Color Mode of RAMDAC operation as shown in
the following table “Color Mode Select” (default
is 0 at power up).
Functional Description
This section describes the register address and bit definition
for the RAMDAC and the Frequency Synthesizer sections.
Bit 3-2
Bit 1
(Reserved) Set to ‘0’ for future compatibility.
Color Palette
Command Register
(RS0-RS2 = 011)
(RS0-RS1 = 01 with hidden flag)
By setting bits 4 and 7-5 in the command register the
ICS5342 can be programmed for different color modes and
the DACs can be turned off for low power operation.
Test Mode - When bit 1 is set checksum accumu-
lation is enabled. If bit 0 is also set the oscillator
and synthesizers are turned off for minimum
noise.
Bit 0
Power Down Mode of RAMDAC - When this bit
is set to 0 (default is 0), the device operates nor-
mally. If this bit is set to 1, the power and clock
to the Color Palette RAM and DACs are turned
off. The data in the Color Palette RAM are still
preserved. The CPU can access without loss of
data by internal automatic clock start/stop con-
trol. The DAC outputs become the same as
BLANK* (sync) level output during power down
mode. This bit does not affect the PLL clock syn-
thesizer function unless test mode is enabled.
Command Registers
7
6
5
4
3
2
1
0
2
1
0
3
Reserved = 0
Test mode Snooze
Color Mode Select
8-BIT INTERFACE
Mode
CM3
CM2
CM1
CM0
Clock Cycles/
Number
(CR4)
(CR7)
(CR6)
(CR5)
Color Mode
Pixel Bits
0
0
0
0
0
8-bit Pseudo Color With Palette (default)
15-bit Direct Color With Bypass (Hi-Color)
24-Bit True Color With Bypass (True Color)
16-bit Direct Color With Bypass (XGA)
15-bit Direct Color With Bypass (hi-color)
15-bit Direct Color With Bypass (Hi-Color)
15-bit Direct Color With Bypass (Hi-Color)
24-bit True Color With Bypass (True Color)
1
2
3
2
2
2
2
3
1
3
2
1
1
2
3
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
16-BIT INTERFACE
Mode
Number
CM3
(CR4)
CM2
(CR7)
CM1
(CR6)
CM0
(CR5)
Clock Cycles/
Pixel Bits
Color Mode
4
1
0
0
0
Multiplexed 16-bit Pseudo Color With Palette
15-bit Direct Color With Bypass (Hi-Color)
16-bit Direct Color With Bypass (XGA
24-bit True Color With Bypass (True Color)
24-bit Packed True Color With Bypass
(true-color)
1/2
1
1
2
3/2
5
6
7
8
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
1
1
1
1
1
1
0
1
1
1
0
1
Reserved
Reserved
Reserved
14
ICS5342
GENDAC
16-Bit Color - Mode 2
Color Modes
SECOND BYTE
FIRST BYTE
The nine selectable color modes are described here. Four are
eight-bit and five are 16-bit wide pixel input. Color Modes 0-3
are 8-bit interfaces with bits P0-P7; P8-P15 are “don’t care”
bits.
P P P P P P P P P P P P P P P P
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
7 6 5 4 3 7 6 5 4 3 2 7 6 5 4 3
RED
GREEN
BLUE
Mode 0: 8-bit Pseudo Color (one clock per pixel). This mode 2LSB = set to zero (green)
is the 8-bit per pixel Pseudo Color mode. In this mode, inputs 3LSB = set to zero (blue, red)
P0-P7 are the pixel address for the color palette RAM and are
latched on the rising edge of every PCLK. This is the default Mode 3: (24-bit per pixel True Color Mode). This mode is the
mode on power up and it is selected by setting bits CR7-CR4 24-bit per pixel bypass mode. The three bytes of data are
to 0000.
latched on three successive PCLK edges and the first byte is
synchronized by the rising edge of BLANK*. In this mode,
each of the colors are 8-bit wide and the DAC is an 8-bit wide
DAC. The first byte is blue followed by green and red. This
mode can be selected by setting bits CR7-CR4 to 0100 or
1110. The DAC outputs changes every three cycles and the
pipeline delay from the first byte to output is five cycles.
8-bit Pseudo Color
- Mode 0
PIXEL BYTE
P P P P P P P P
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
LUT ADDRESS
24-bit Color - Mode 3
THIRD BYTE
SECOND BYTE FIRST BYTE
Mode 1: (15-bit per color bypass Hi-Color mode). This mode
is the 15-bit per pixel bypass mode. In this mode, inputs P0-P7
are the color DATA and are input directly to the DAC, by-
passing the color palette. The two bytes of data are latched in
two successive PCLK rising edges. ICS5342 supports only
the two clock mode and does not support the mode where the
data are latched on the rising and the falling edges. For com-
P P P P P P P P P P P P P P P P P P P P P P P P
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
RED
GREEN
BLUE
16 bit Color Modes
patibility, the 15/16 one clock modes are selected as two clock Modes 4 - 8 use the 16-bit pixel interface.
modes in this chip. The low-byte, high byte synchronization
is internally done by the rising edge of BLANK*. Each color Mode 4: (8-bit Pseudo Color two pixels per clock) In this
is 5-bit wide and is packed into two bytes as shown below. mode, inputs P0-P15 are latched on the rising edge of every
This mode can be selected by setting bits CR7-CR4 to 0010, PCLK. P0-7 and P8-P15 are used for successive addresses for
1000 or 1010.
the palette RAM using an internal clock (ICLK) that runs at
twice the PCLK frequency. The DAC outputs change twice
for every PCLK and the pipeline delay from the first word to
output is one and one half cycles. This mode can be selected
by setting bits CR7-CR4 to 0001.
15-Bit Color - Mode 1
SECOND BYTE FIRST BYTE
P P P P P P P P P P P P P P P P
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
X 7 6 5 4 3 7 6 5 4 3 7 6 5 4 3
Multiplexed 8-bit Pseudo Color Word
- Mode 4
X RED
GREEN
BLUE
PIXEL WORD
3LSB = set to zero
P P P P P P P P P P P P P P P P
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0
Mode 2: (16-bit per pixel bypass XGA mode). This mode is
the 16-bit per pixel bypass mode and the P0-P7 inputs to go to
the DAC directly, bypassing the color palette. The 2 bytes
data is latched on two successive rising edges and the low-
byte, high-byte synchronization is internally done by the ris-
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
2nd PIXEL
ADDRESS
1st PIXEL
ADDRESS
ing edge of BLANK*. In this mode, blue and red colors are 5 Mode 5: (16-bit pixel interface, 15-bit per color bypass Hi-
bits wide and green is 6 bits wide. The 2 bytes of data are Color Mode) In this mode inputs P0-P15 are the color data
packed as shown below. This mode can be selected by setting and are input directly to the DAC, bypassing the color palette.
bits CR7-CR4 to 0110 or 1100.
The data is latched by the rising edge of PCLK and is pipe-
15
ICS5342
GENDAC
24-Bit Direct Color Word - Mode 7
lined to the DAC. The pipeline delay from input to DAC out-
put is three PCLK cycles. Each color is 5-bit wide as shown
below. This mode is selected by setting bits CR7-CR4 to
0011.
FIRST WORD
P P P P P P P P P P P P P P P P
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0
15-Bit Color Word - Mode 5
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
PIXEL WORD
GREEN
BLUE
P P P P P P P P P P P P P P P P
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0
SECOND WORD
P P P P P P P P P P P P P P P P
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0
X 7 6 5 5 4 7 6 5 4 3 7 6 5 4 3
X
RED
GREEN
BLUE
X X X X X X X X 7 6 5 4 3 2 1 0
3LSB = set to zero
IGNORED
RED
Mode 6: (16-bit pixel interface, 16-bit per color bypass XGA Mode 8: (16-bit pixel interface packed 24-bit per color bypass
mode) In this mode input P0-P15 are the color data and are in- TRUE color mode) In this mode inputs P0-P15 are the color
put directly to the DAC bypassing the color palette. The data data and are input directly to the DAC bypassing the color pal-
is latched by the rising edge of PCLK and is pipelined to the ette. Three words are latched on three successive rising edges
DAC. The pipeline delay, from input to DAC output, is three of PCLK to form two successive 24-bit DAC inputs. The 16-
PCLK cycles. In this mode Blue and Red colors are 5 bits bit first word and the lower byte of the second word from the
wide, and Green is 6 bits wide. This mode is selected by set- first 24-bit pixel input and the second byte of the second word
ting bits CR7-CR4 to 0101.
with the 16 bits of the third word from the second 24-bit pixel
input. This cycle repeats every three cycles. The three-word
synchronization is internally done by the rising edge of
BLANK*. The pipeline delay from latching of first word to
DAC output is 3 1/2 cycles and each of the colors are 8-bits
wide and DAC is 8-bit wide DAC. The first byte is Blue fol-
lowed by Green and Red. This mode is selected by setting bits
CR7-CR4 to 1001.
16-Bit Color Word - Mode 6
PIXEL WORD
P P P P P P P P P P P P P P P P
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0
7 6 5 4 3 7 6 5 4 3 2 7 6 5 4 3
RED
GREEN
BLUE
Packed 24-bit Word - Mode 8
1st DAC Cycle
2LSB = set to zero (GREEN)
3LSB = set to zero (BLUE, RED)
SECOND WORD
FIRST WORD
P P P P P P P P P P P P P P P P P P P P P P P P
7 6 5 4 3 2 1 0 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Mode 7: (16-bit pixel interface, 24-bit per color bypass
TRUE color mode) In this mode inputs P0-P15 are the color
data and are input directly to the DAC bypassing the color pal-
ette. Two words are latched on two successive rising edge of
PCLK to form the 24-bit DAC input. The first word and the
lower byte of the second word form the 24-bit pixel input to
the DAC. The higher byte of the second word is ignored. The
low and high word synchronization is internally done by the
rising edge of BLANK*. The pipeline delay from latching of
the first word to DAC output is 4 cycles and each pixel is two
pixel clocks wide. In this mode, each of the colors are 8-bits
wide and the DAC is 8-bit wide DAC. The first byte is Blue
followed by Green and Red. This mode is selected by setting
bits CR7-CR4 to 0111.
RED
GREEN
BLUE
2nd DAC Cycle
THIRD WORD
SECOND WORD
P P P P P P P P P P P P P P P P P P P P P P P P
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 9 8
5 4 3 2 1 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
RED GREEN BLUE
5 4 3 2 1 0
16
ICS5342
GENDAC
Frequency Generators
PLL Control Register
The ICS5342 clock synthesizer can be reprogrammed through Bits in this register determine internal or external CLK0 se-
the microprocessor interface for any set of frequencies. This lect.
is done by writing appropriate values to the PLL Parameter
Register Bank (See following table: “PLL Parameter Regis-
ters”).
PLL Control Register
7
6
5
4
3
2
1
0
(RV)= (RV)= ENBL CLK1 (RV)= Internal Select
INCS SEL X
0
0
0
X
X
PLL Address Registers
Bit 7,6, 3 Reserved, set to ‘0’ for future compatibility.
The address of the parameter register is written to the PLL ad-
dress registers before accessing the parameter register. This
register is accessed by register select pins RS2-RS0 = 100 or
111.
Bit 5
Enable Internal Clock Select (INCS) for CLK0.
When this bit is set to 1, the CLK0 output fre-
quency is selected by bits 2-0 in this register.
External pins CS0-CS2 are ignored.
PLL Address Register
Bit 4
Clk1 Select when this bit is set to 0, fA is
selected. When it is set to 1, fB is selected. The
default is 0 for fA selected at power up.
7 6 5 4 3 2 1 0
PLL Register Adr.
7 6 5 4 3 2 1 0
Bit 2 - 0 Internal Clock Select for CLK0 (INCS). These
three bits select the CLK0 output frequency if bit
5 of this register is on. They are interpreted as an
octal number, n, that selects fn. Default selects f0.
PLL Parameters Registers
There are sixteen registers in the PLL parameter register (ta-
ble 5). Registers 00 to 07 are for the CLK0 selectable frequen-
cy list, Register 0A and 0B for CLK1 programmable
frequency and register 0E is the PLL control register.
PLL Data Registers
The CLK0 and CLK1 output frequency is determined by the
parameter values in this register. These are two-byte registers;
the first byte is the M-byte and the second the N-byte.
PLL Parameter Registers
Index R/W
Register
M-Byte PLL Parameter Input
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/-
R/W
R/W
R/W
R/-
CLK0 f0 PLL Parameters
CLK0 f1 PLL Parameters
CLK0 f2 PLL Parameters
CLK0 f3 PLL Parameters
CLK0 f4 PLL Parameters
CLK0 f5 PLL Parameters
CLK0 f6 PLL Parameters
CLK0 f7 PLL Parameters
(Reserved) = 0
CLK1 fA PLL
CLK1 fB PLL
(Reserved) = 0
(Reserved) = 0
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes
(2 bytes)
(2 bytes)
(2 bytes
(2 bytes)
(2 bytes)
(1-byte)
(2 bytes)
The M-byte has a 7-bit value (1-127) which is the feedback
divider of the PLL.
M-Byte
7
6
5
4
3
2
1
0
Reserved
= 0
M-Divider Value
X
X
X
X
X
X
X
N-Byte PLL Parameter Input
The N-byte contains two parameter values. N1 sets a 5-bit val-
ue (1-31) for the input pre scalar and N2 is a 2-bit code for se-
lecting 1, 2, 4, or 8 post divide clock output.
N-Byte PLL Parameter Input
R/-
R/W
R/-
(Reserved) = 0
PLL Control Register
(Reserved) = 0
7
6
5
4
3
2
1
0
Reserved N2 - Code
= 0
N1-Divider Value
X
X
X
X
X
X
X
17
ICS5342
GENDAC
N2 Post Divide Code
Additional Information on Programming
If mode 4 is set in the command register, CR7-CR4 bits equal the Frequency Generator section of the
0001, and the N2 code must be 10.
GENDAC
N2 Post Divide Code
When programming the GENDAC PLL parameter registers,
there are many possible combinations of parameters which
will give the correct output frequency. Some combinations are
better than others, however. Here is a method to determine
how the registers need to be set:
N2 Code
Divider
00
01
10
11
1
2
4
8
The key guidelines come from the operation of the phase
locked loop, which has the following restrictions:
The block diagram of the PLL clock synthesizer is shown in
figure 3.
1. 2 MHz < f REF < 25 MHz This refers to the input refer-
ence frequency. Most users simply connect a 14.318
MHz crystal to the crystal inputs, so this is not a prob-
lem.
Based on the M and N values, the output frequency of the
clocks is given by the following equation:
(M + 2)FREF
2N2(N1 + 2)
f REF
--------------------------------
=
FOUT
----------------
2. 600KHz ≤
≤ 8 MHz This is the frequency input to
N1 + 2
the phase detector.
M and N values should be programmed such that the frequen-
cy of the VC0 is within the optimum range for duty cycle, jit-
ter and glitch free transition. Optimum duty cycle is achieved
by programming N2 for values greater than unity. See the next
section for a programming example.
M + 2
N1 + 2
----------------
3. 60MHz ≤
f REF ≤ 270 MHz This is the VCO
frequency. In general, the VCO should run as fast as pos-
sible, because it has lower jitter at higher frequencies.
Also, running the VCO at multiples of the desired fre-
quency allows the use of output divides, which tends to
improve the duty cycle.
Programming Example
Suppose an output frequency of 25.175 MHz is desired. The
reference crystal is 14.318 MHz. The VCO should be targeted
to run in the 60 to 270 MHz range, so choosing a post divide
of 4 gives a VCO frequency of:
4. f CLK0 and f CLK1 ≤ 35 MHz This is the output fre-
quency.
These rules lead to the following procedure for determining
the PLL parameters, assuming rules 1 and 4 are satisfied.
4 × 25.175 = 101.021 MHz
A. Determine the value of N2 (either 1, 2, 4 or 8) by select-
ing the highest value of N2, which satisfies the condition
N2* fCLK < 270 Mhz.
From the table in the previous section, we find N2 = 2 Substi-
N2
tuting F
= 14.318 and 2 = 4 into the clock frequency
REF
equation in the previous section:
25.175
---------------
14.318
M + 2
= ----------------
N1 + 2
2 N2 f OUT
4
M + 2
N1 + 2
B. Calculate:
---------------- = -----------------------
f REF
By trial and error:
C. Now (M+2) and (N1+2) must be found by trial and error.
With a 14.318 MHz reference frequency, there will gen-
erally be a small output frequency error due to the reso-
lution limit of (M+2) and (N1+2). For a given frequency
tolerance, several different (M+2) and (N1+2) combina-
tions can usually be found. Usually, a few minutes trying
M + 2 = 127 M = 125
N1 + 2 = 18 N1 = 16
so the registers are:
M = 125d = 1 1 1 1 1 0 1 b
N = 0 & N2 code & N1 = 0 & 1 0 & 1 0 0 0 0
N = 0 1 0 1 0 0 0 0 b
18
ICS5342
GENDAC
out numbers with a calculator will produce a workable
combination. Multiplying possible values of (N1+2) by
the desired ratio will indicate approximately the value of
M. This method is shown in the example below. A pro-
gram could be written to try all possible combinations of
(M+2) and (N1+2) (3937 possible combinations). Dis-
card those outside the error band, and select from those
remaining by giving preference to ratios which use lower
values of (M+2). Lower values of (M+2) and (N1+2)
provide better noise rejection in the phase locked loop.
C. Setting (N1+2) = 3,4, ...12, 13 and performing some
simple calculations yields the following table: (Notethat
N1 cannot be 0).
The ratio 83/9 is closest. Thus:
(N2+2) = 9
N2=7
(M+2) = 83
M = 81
Example: Suppose you have a 14.318 MHz reference crystal The M-byte PLL parameter word is simply 81 in binary, plus
and want an output frequency of 66 MHz. You want to limit bit 7 (which must be set to 0), or 01010001. The N-byte PLL
the VCO frequency to 240 Mhz and have an error of no great- parameter word is N2 code (01) concatenated with 5 bits of
er than 0.5%. What are the values of the PLL data registers?
A. 66*8 = 528 > 250 — VCO speed too high
66*4 = 264 > 250 — VCO speed too high
N2 in binary (00111), or 00100111. Once again, bit 7 must be
zero.
The combination with the least frequency error was chosen,
but several other combinations are within the 0.5% tolerance.
Because the lowest value of (M+2) offers the best damping,
the 37/4 combination will have the best power supply rejec-
tion. This results in lower jitter due to external noise.
66*2 = 132 < 250 — VCO speed OK, N2 = 2, N2 code =
01 from the Post Divide Code table in the PLL Data
Registers section.
B. 132/14.31818 = 9.219 This is the desired frequency mul-
tiplication ratio.
Example Calculation of PLL Data Register Values
(N1 + 2)
(N1 + 2) *9.219
rounded (=M + 2)
Actual Ratio
Percent Error
3
4
5
6
7
8
9
10
11
12
13
27.657
36.876
46.095
55.314
64.533
73.752
82.971
92.19
28
37
46
55
65
74
83
92
9.33
9.25
9.20
9.17
9.29
9.25
9.22
9.20
9.18
9.25
9.23
-1.23
-0.34
0.21
0.57
-0.72
-0.34
-0.03
0.21
0.40
-0.34
-0.13
101.409
110.628
119.847
101
111
120
19
ICS5342
GENDAC
N2
COUNTER
F
LOOP
FILTER
ref
PHASE
DETECT
CHARGE
PUMP
VCO
1/(N1+2)
1/(M1+2)
5342_07
PLL Clock Synthesizer Block Diagram
Video Clock Selection Table
External Select
(Internal Select PLL Control Register)
CLK 0
Frequency
CS2
CS1
CS0
BIT 2
BIT 1
BIT 0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
f0
f1
f2
f3
f4
f5
f6
f7
20
ICS5342
GENDAC
PCLK
P0-P7
A
B
C
D
E
F
G
H
I
J
K
BLANK
RED
C
G
G
B
B
A
F
F
BLANK
BLANK
BLANK
A
A
C
C
GREEN
BLUE
G
B
F
5342_8
System Timing - Pseudo Color, Mode 0
tCHCL
tCLCH
tCHCH
PLCK
tPVCH
tCLPX
G
H
I
J
K
E
F
tBVCH
tCHBX
BLANK
RED
t
CHAV C
G
B
B
F
F
A
A
BLANK
tCHAV
G
G
C
BLANK
BLANK
tCHAV
A
C
F
B
BLUE
5342_09
Detailed Timing Specifications – Pseudo Color, Mode 0
21
ICS5342
GENDAC
PCLK
1
2
3
4
5
6
7
BLANK
LOW BYTE
A
HIGH BYTE
A
LOW BYTE
B
HIGH BYTE
B
P0-P7
B
B
A
DAC-RD
DAC-GR
DAC-BL
A
A
B
5342_10
System Timing Bypass- 15(5/6/5) Modes 1,2
0ns
25ns
50ns
3
75ns
100ns
8
125ns
150ns
PCLK
1
2
4
5
6
7
9
A
B
C
BLANK
P0-P7
BL
GR RD BL
GR
RD
DAC-BL
DAC-GR
A
C
DAC-RD
B
5342_11
System Timing Bypass True Color 24 (8,8,8) Mode 3
22
ICS5342
GENDAC
PCLK
ICLK
1
1
1
1
1
1
1
A
B
C
D
E
F
G
H
J
L
N
P
P0-P7
K
M
P8-P15
BLANK
C
L
K
J
D
D
A
A
B
B
RED
GREEN
BLUE
BLANK
J
J
L
L
C
BLANK
BLANK
C
A
D
B
K
5342_12
System Timing - 8-bit Pseudo Color, Mode 4
1
2
3
4
5
6
7
PCLK
P0-P7
A
B
C
D
E
F
G
H
BLANK
RED
B
B
A
BLANK
BLANK
BLANK
A
A
GREEN
BLUE
B
5342_13
System Timing - 16-bit Color, Mode 5(5,5,5) and 6((5,6,5)
23
ICS5342
GENDAC
1
2
3
4
5
6
7
PCLK
P0-P7
Ab
Ag
Ar
--
Bb
Bg
Br
--
Cb
Cg
Cr
--
Db
Dg
Dr
--
BLANK
RED
A
A
BLANK
GREEN
BLUE
BLANK
A
BLANK
5342_14
System Timing - 16-bit Direct True Color, Mode 7
1
2
3
4
5
6
7
PCLK
P0-P7
AL
AM
AU
BL
BM
BU
CL
CM
CU
DL
DM
DU
EL
EM
EU
FL
FM
FU
GL
GM
BLANK
RED
B
B
A
BLANK
BLANK
BLANK
BLANK
A
A
BLANK
BLANK
GREEN
BLUE
B
5342_15
System Timing - 24-bit Packed Color, Mode 8
24
ICS5342
GENDAC
tWLWH
WR*
tSVWL
tWLSX
RS0-RS1
D0-D7
tDVWH
tWHDX
Basic Write Cycle Timing
tRLRH
RD*
tSVRL
tRLSX
RS0-RS1
tRLQV
tRHQX
tRHQZ
D0-D7
tRLQX
Basic Read Cycle Timing
5342_16
tWHWL1
tWHRL1
WR*
RD*
RS0
RS1
Write to Pixel Mask Register Followed by Write
Write to Pixel Mask Register Followed by Read
WR*
tRHWL1
tRHRL1
RD*
Read from Pixel or Pixel Address Register
(Read or Write) followed by Read
Read from Pixel or Pixel Address Register
(Read or Write) followed by Write
5342_17
Read-Write Timing
25
ICS5342
GENDAC
WR*
tWHRL1
RD*
RS0
RS1
RS2
ADDRESS
ADDRESS+1
D0-D7
5342_18
Write and Read Back Pixel Address Register (Read Mode)
WR*
t
WHRL3
RD*
RS0
RS1
RS2
ADDRESS
D0-D7
ADDRESS
5342_19
Write and Read Back Pixel Address Register (Write Mode)
26
ICS5342
GENDAC
WR*
tWHRL3
tRHRL1
tRHRL1
tRHRL2
RD*
RS0
RS1
RS2
D0-D7
ADDRESS
ADDRESS+2
GREEN
BLUE
RED
5342_20
Read Color Value then Pixel Address Register (Read Mode)
tWHWL1
tWHWL1
tWHWL1
WR*
RD*
tWHRL2
RS0
RS1
RS2
D0-D7
ADDRESS
GREEN
BLUE
RED
5342_21
Color Value Write Followed by any Read
27
ICS5342
GENDAC
tWHWL1
tWHWL1
tWHWL1
tWHWL2
WR*
RD*
RS0
RS1
RS2
ADDRESS
D0-D7
GREEN
BLUE
RED
5342_22
Color Value Write Followed by any Write
WR*
t
t
t
t
RHRL2
WHRL3
RHRL1
RHRL1
RD*
RS0
RS1
RS2
ADDRESS
D0-D7
GREEN
BLUE
RED
5342_23
Color Value Read Followed by any Read
28
ICS5342
GENDAC
WR*
t
t
t
t
RHWL2
WHRL3
RHRL1
RHRL1
RD*
RS0
RS1
RS2
ADDRESS
D0-D7
GREEN
BLUE
RED
5342_24
Color Value Read Followed by any Write
WR*
t
WHRL3
RD*
RS0
RS1
RS2
ADDRESS
D0-D7
ADDRESS
5342_25
Write and Read back PLL Address Register (Write Mode)
29
ICS5342
GENDAC
WR*
tWHRL3
RD*
RS0
RS1
RS2
ADDRESS
ADDRESS+1
D0-D7
5342_26
Write and Read back PLL Address Register (Read Mode)
WR*
t
t
t
t
RHRL2
WHRL3
RHRL1
RHRL1
RD*
RS0
RS1
RS2
D0-D7
PLL HIGH
ADR+1
PLL ADDRESS
PLL LOW
5342_27
Read Two bytes PLL Register then PLL Address Register
30
ICS5342
GENDAC
WR*
t
t
t
t
RHRL2
WHRL3
RHRL1
RHRL1
RD*
RS0
RS1
RS2
ADR+1
D0-D7
PLL
ADDRESS
5342_28
Read One Byte PLL Register then PLL Address Register
RED
GREEN
0.335V
BLUE
tS0D
SENSE
5342_29
Monitor SENSE Signal
31
ICS5342
GENDAC
Recommended Layout
LOCATE NEAR
CONTROLLER
LOCATE NEAR
CONTROLLER
R4
R4
R1
C2
R2
C2
R2
CGND
PCLK
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
CLK1
R5
GENDAC II
ICS5342
C2
VAA
XVDD 50
XOUT
49
48
47
46
45
44
XIN
Y1
XGND
VREF
DGND
DGND
C2
C1
C2
C2
VAA
VAA
R3
C1
-
FB1
C3
-
VIA to power plane
VIA to ground plane
C1 0.047 µF chip capacitor
C2 0.1 µF chip capacitor
C3 10 µF tantalum capacitor
FB1 ferrite bead, Fair-Rite 2743019447
R1 33 ohm
R2 100 ohm
R3 141 ohm, 1%
R4 220 ohm
R5 560 ohm
Y1 parallel resonant crystal cut for C = 12 pF
5342_30
L
Board Layout and Analog Signal Consider- Power Supply
ations
As a high speed CMOS device, the GENDAC may draw large
The high performance of the GENDAC is dependent on care- transient currents from the power supply. It is necessary to
ful PC board layout. The use of a four layer board (internal adopt high-frequency board-layout and power-distribution
power and ground planes, signals on the two surface layers) is techniques to assure proper operation of the GENDAC. This
recommended. The ground plane layer should be closest to the will also minimize radio frequency interference (RFI). DAC
component side of the board. The layout following this sec- to DAC crosstalk can also be attributed to a high impedance
tion shows a suggested configuration.
power supply.
32
ICS5342
GENDAC
Note the power plane is not separated into analog and digital on the GENDAC. The effect this will have is to compromise
supply regions. The power and ground planes are continuous, the low time and duty cycle of the output clocks.
not split. Power is supplied to the analog power pins through The PCB traces between the outputs of the TTL devices driv-
the ferrite bead, and bypassed at the power entry point by C3, ing the GENDAC and the input to the GENDAC behave like
a 10 µF tantalum capacitor. Analog power connections should low impedance transmission lines. The trace is driven from a
be routed as shown in the diagram. They may be routed on the low impedance source and terminated with a high impedance.
back side so the analog signals are routed without vias. Power In accordance with transmission line principles, signal transi-
pins 9 and 43 should be connected to digital power. Power tions will be reflected from the high impedance input to the
pins 27, 41 and 50 are connected to analog power (VAA). Ce- device. Similarly, signal transitions will be inverted and re-
ramic decoupling capacitors (indicated by C1 and C2) should flected from the low impedance TTL output. Termination is
be placed as close to the GENDAC as possible. The power necessary to reduce or eliminate ringing; particularly the un-
traces should be routed through the capacitor pads and the dershoot caused by reflections. Termination may either be se-
ground vias should not be shared. The rule is: one pad, one ries or parallel. Series and parallel termination is the
via. The GENDAC analog ground pins should have multiple recommended technique to use. This is accomplished by plac-
vias to the ground plane, if possible.
ing a resistor in series with the signal at the output of the clock
To supply the transient currents required, the impedance in driver. The resistor matches the output buffer impedance to
the decoupling path should be kept to a minimum. It is just as that of the transmission line. At the far end of the line another
important that the connection between the capacitor ground resistor is added to terminate the transmission line to VCC.
pad and the ground plane be short and direct. It is recommend- To minimize reflections, some experimentation is necessary
ed that the decoupling capacitance between V
and GND to find the proper value to use for the series termination. Gen-
DD
should be a 0.047 µF to 0.1 µF high frequency capacitor. Chip erally, a series resistor with a value around 75Ω, and a parallel
capacitors have the lowest lead inductance and are highly rec- resistor of 330Ω will be satisfactory. Since each design will
ommended. 0.047 µF chip capacitors are more effective at fre- result in a different trace impedance, a resistor of a predeter-
quencies above 80 MHz than other values in the range of mined value may not properly match the signal path imped-
0.022 µF to 0.1 µF. All supply pins must have a ceramic ca- ance. The proper value of resistance should be found
pacitor connected. A tantalum capacitor with a value between empirically.
10 µF and 22 µF is recommended to decouple low frequen-
cies. To further reduce power-supply noise, a ferrite bead may
be added in series with the positive supply to form a low pass
filter, as shown in the layout example. Power and ground trac-
es to the GENDAC should be 50 mils wide whenever possi-
ble.
Analog Signals
All analog and digital I/O lines are not shown. Analog signals
(DAC outputs, V , R ) should only be routed on the top
REF SET
side of the board. DAC output termination resistors should be
located as close as possible to the GENDAC for best signal
quality. Doing this will also reduce RFI.
Digital Input Information
To minimize differential ground noise between components
on the board, the impedance in the ground supply between the
GENDAC and the digital devices driving it should be mini-
mized. This or a high impedance ground trace on the control-
ler may cause false signals to the GENDAC. This can appear
as glitches on edge sensitive inputs such as RD*, WR*, and
STRB. Splitting the ground plane exacerbates this problem.
The combination of series impedance in the ground supply to
the GENDAC and transients in the current drawn by the de-
vice, will appear as voltage differences across the GND pins
33
ICS5342
GENDAC
34
ICS5342
GENDAC
35
ICS5342
GENDAC
Package Outline
PIN 1 IDENTIFIER
0.045
0.045
GENDAC II
ICS5342
0.890 - 0.930
(22.61 - 23.62)
0.013 - 0.021
(0.33 - 0.53)
0.985 - 0.995
(25.02 - 25.27)
0.020
(0.51)
0.102
(2.59)
0.950 - 0.958
0.165 - 0.180
(4.20 - 4.57)
(24.13 - 24.33)
LEAD PITCH 0.050 TYPICAL
DIMENSIONS: INCHES
(MILLIMETERS)
68 PIN PLCC
5342_31
Package Detail
36
相关型号：
ICS542M
Low Skew Clock Driver, 542 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, SOIC-8
IDT
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