ICS548-05AII [ICSI]
MP3 Audio Clock; MP3音频时钟
| 型号： | ICS548-05AII |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | MP3 Audio Clock |
| 文件： | 总4页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY INFORMATION
ICS548-05A
MP3 Audio Clock
Features
Description
The ICS548-05 is a low cost, low jitter, high
performance clock synthesizer designed to
produce audio sampling rates for MP3 systems.
Using ICS’ patented analog/digital Phase-Locked
Loop (PLL) techniques, the device uses an
inexpensive 3.6864 MHz crystal or clock input to
exactly produce all of the popular audio sampling
frequencies. Power down modes allow the chip to
be turned off completely, or the PLL and audio
clock output to be turned off separately.
• Packaged in 16 pin TSSOP
• Ideal for Cirrus Logic’s MP3 chips
• Replaces multiple oscillators
• 3.3V (will work down to 2.7V) or 5V operation
• Uses an inexpensive 3.6864 MHz crystal or
clock input
• Supports 32 kHz, 44.1 kHz, 48 kHz, and 96 kHz
audio sampling rates
ICS manufactures the largest variety of
multimedia clock synthesizers for all applications.
Consult ICS to eliminate VCXOs, crystals and
oscillators from your board.
• Provides 128fs and 256fs clocks
• Zero ppm synthesis error
• Includes Power Down features
• Advanced, low power, sub-micron CMOS process
Block Diagram
4
S3:S0
PLL/Clock
Synthesis
Circuitry
Output
Buffer
REFEN
PDCLK
CLK
X1
Crystal
Oscillator
Output
Buffer
3.6864 MHz
crystal or clock
REFOUT
X2
Optional crystal capacitors
MDS 548-05 AC
1
Revision 032900
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
PRELIMINARY INFORMATION
ICS548-05A
MP3 Audio Clock
Pin Assignment
Output Clock Select Table
S3
S2
S1
S0
Input (MHz)
Pins 1, (16)
3.6864
CLK (MHz)
Pin 9
ICS548-05A
Pin 7 Pin 8 Pin 12 Pin 13
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2.8224
3.072
1
2
3
4
5
6
7
8
16 X2
X1/ICLK
VDD
VDD
REFEN
GND
GND
S3
3.6864
15 DC
14 REFOUT
13 S0
3.6864
4.096
3.6864
5.6448
6.144
3.6864
Turns off PLL and stops CLK low
12 S1
3.6864
3.6864
3.6864
3.6864
8.192
11.2896
12.288
2.048
PDCLK
11
10 DC
9
S2
CLK
16 pin TSSOP
Power Down Clock Select Table
REFEN PDCLK Power Down Selection Mode
Pin 4
Pin 11
0
0
1
1
0
1
0
1
The entire chip is off.
PLL and CLK output run, REFOUT low.
REFOUT running, PLL off, CLK low.
All running.
Key: 0 = connect directly to GND
1 = connect directly to VDD
Pin Descriptions
Number
Name
X1/ICLK
VDD
REFEN
GND
S3
Type Description
1
2, 3
4
XI
P
I
Crystal connection. Connect to a 3.6864 MHz crystal, or input clock.
Connect to +3.3V or +5V. All VDDs must be same.
Reference Clock Enable. See above table.
5, 6
7
P
I
Connect to ground.
Frequency select pin 3. Determines clock outputs per table above.
Frequency select pin 2. Determines clock outputs per table above.
Audio clock output set by status of S0-S3. See table above.
Don't Connect. Do not connect anything to these pins.
Power Down Clock. See above table.
8
S2
I
9
CLK
O
-
10, 15
11
12
13
14
16
DC
PDCLK
S1
I
I
Frequency select pin 1. Determines clock outputs per table above.
Frequency select pin 0. Determines clock outputs per table above.
Buffered 3.6864 MHz oscillator output clock. Controlled by REFEN.
Crystal connection. Connect to a 3.6864 MHz crystal, or leave unconnected for clock.
S0
I
REFOUT
X2
O
XO
Key: I = Input; O = output; P = power supply connection; XI, XO = crystal connections
The input pins S3:S0 lack pull-ups, so they cannot be left floating. Tie directly to VDD or GND. For a
clock input, connect the input to X1, and leave X2 unconnected (floating).
MDS 548-05 AC
2
Revision 032900
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
PRELIMINARY INFORMATION
ICS548-05A
MP3 Audio Clock
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
VDD+0.5
70
V
V
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage temperature
Referenced to GND
Max of 10 seconds
-0.5
0
°C
°C
°C
260
-65
150
DC CHARACTERISTICS (VDD = 3.3V unless noted)
Core Operating Voltage, VDD
2.7
5.5
(VDD/2)-1
0.8
V
V
Input High Voltage, VIH, X1/ICLK pin
Input Low Voltage, VIL, X1/ICLK pin
Input High Voltage, VIH
Clock input only
Clock input only
(VDD/2)+1
VDD/2
VDD/2
V
2
V
Input Low Voltage, VIL
V
Output High Voltage, VOH
Output Low Voltage, VOL
IOH=-12mA
IOL=12mA
2.4
V
0.4
V
Output High Voltage, VOH, CMOS level IOH=-4mA
VDD-0.4
V
Operating Supply Current, IDD
Power Down Supply Current, IDDPD
Short Circuit Current
No Load
4
5
mA
µA
mA
pF
ppm
No Load
CLK output
S0, S1, S2, S3, PDCLK
All selections
±50
7
Input Capacitance
Frequency synthesis error
0
AC CHARACTERISTICS (VDD = 3.3V unless noted)
Input Crystal or Clock Frequency
3.6864
50
MH z
ns
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Start-up Time
0.8 to 2.0V
2
2.0 to 0.8V
2
ns
At VDD/2
40
60
10
%
VDD=3V to CLK stable
ms
ps
Maximum Absolute Jitter, short term
One sigma jitter
±250
70
ps
Note: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
External Components/ Application Information
The ICS548-05 requires a minimum number of external components for proper operation. A decoupling
capacitor of 0.01µF should be connected between VDD and GND on pins 3 and 5, as close to the
ICS548-05 as possible. Other VDDs can be connected to pin 3. A series termination resistor of 33 Wmay
be used for each clock output. If REFOUT is not used, then REFEN should be connected to ground. The
input crystal must be connected as close to the chip as possible. The input crystal should be fundamental
mode, parallel resonant. For exact accuracy of the output frequencies, the crystal can be tuned with two
identical capacitors to ground, as shown on the block diagram. The value of these two crystal caps should be
equal to (C -6)*2, where C is the crystal load (or correlation) capacitance.
L
L
MDS 548-05 AC
3
Revision 032900
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
PRELIMINARY INFORMATION
ICS548-05A
MP3 Audio Clock
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC publication no. 95.)
16 pin TSSOP
Inches
Symbol Min
Millimeters
Max
Min
Max
A
A1
b
--
0.047
--
1.19
0.15
0.30
0.20
5.11
0.002 0.006
0.007 0.012
0.0035 0.008
0.193 0.201
.025 BSC
0.05
E1
E
0.18
c
0.09
D
e
4.90
INDEX
AREA
0.65 BSC
6.40 BSC
4.29
1
2
E
.252 BSC
E1
L
0.169 0.177
0.018 0.030
4.50
0.76
0.46
D
A
A1
c
b
L
e
Ordering Information
Part/Order Number
ICS548G-05
Marking
548G-05
548G-05
Shipping packaging
tubes
Package
Temperature
0-70 °C
16 pin TSSOP
16 pin TSSOP
ICS548G-05T
tape and reel
0-70 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 548-05 AC
4
Revision 032900
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
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