ICS551 [ICSI]
1 to 4 Clock Buffer; 1到4个时钟缓冲器
| 型号： | ICS551 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 1 to 4 Clock Buffer |
| 文件： | 总4页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY INFORMATION
Features
ICS551
1 to 4 Clock Buffer
Description
• Packaged in 8 pin SOIC
The ICS551 is a low cost, high speed single input
to four output clock buffer. Part of ICS’ Clock
Blocks family, this is our lowest cost, small clock
buffer. See the ICS552-01B for a monolithic dual
version of the ICS551 in a 20 pin QSOP.
• Low cost clock buffer
TM
• Low skew (250ps) outputs
• Input/output clock frequency up to 160 MHz
• Operating voltages of 3.0 to 5.5 V
• Non-inverting
ICS makes many non-PLL and PLL based low
skew output devices, as well as Zero Delay Buffers
to synchronize clocks. Contact us for all of your
clocking needs.
• Ideal for networking clocks
• Output Enable mode tri-states outputs
• Full CMOS clock swings with 25mA drive
capability at TTL levels
• Advanced, low power CMOS process
Block Diagram
Q1
Q2
Q3
Q4
ICLK
Output Enable
MDS 551 B
1
Revision 091200
Printed 11/14/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
PRELIMINARY INFORMATION
ICS551
1 to 4 Clock Buffer
Pin Assignment
1
8
7
6
5
OE
ICLK
2
3
4
Q1
Q2
Q3
VDD
GND
Q4
8 pin SOIC
Pin Descriptions
Number
Name
ICLK
Q1
Type Description
1
2
3
4
5
6
7
8
CI
O
O
O
O
P
Clock input. Internal pull-up resistor.
Clock Output 1.
Q2
Clock Output 2.
Q3
Clock Output 3.
Q4
Clock Output 4.
GND
VDD
OE
Connect to ground.
Connect to +3.3 V or +5.0 V.
P
I
Output Enable. Tri-states outputs when low. Internal pull-up resistor.
Key: CI = clock input, I = input, O = output, P = power supply connection
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of
0.01 µF should be connected between VDD on pin 7 and GND on pin 6, and a 33 Wterminating resistor
may be used on each clock output if the trace is longer than 1 inch.
MDS 551 B
2
Revision 091200
Printed 11/14/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
PRELIMINARY INFORMATION
ICS551
1 to 4 Clock Buffer
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
VDD+0.5
70
V
V
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Referenced to GND
Max of 20 seconds
-0.5
0
°C
°C
°C
260
Storage temperature
-65
150
DC CHARACTERISTICS
Operating Voltage, VDD
3
5.5
V
V
Input High Voltage, VIH, IN
Input Low Voltage, VIL, In
Clock input
Clock input
VDD/2 + 1
VDD/2
VDD/2 VDD/2 - 1
V
Input High Voltage, VIH, OE
Input Low Voltage, VIL, OE
Output High Voltage, VOH, 5V
Output Low Voltage, VOL, 5V
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD, 3.3V
Short Circuit Current, 3.3 V
Internal pull-up resistor
2
V
0.8
0.4
V
IOH=-25mA
IOL=25mA
IOH=-8mA
No load, 135 MHz
Each output
All inputs
2.4
V
V
VDD-0.4
V
18
mA
mA
kW
±50
200
AC CHARACTERISTICS
Input Frequency
0
160
160
135
1.5
MH z
MH z
MH z
ns
Output Frequency, 3.3 V
Output Frequency, 5 V
Output Clock Rise Time
Output Clock Fall Time
Propagation Delay
15 pF load. Note 3.
15 pF load. Note 3.
0.8 to 2.0V
2.0 to 0.8V
1.5
ns
At 3.3 V
2
4
3
8
6
ns
At 5.0 V
1.5
ns
Output to output skew
Rising edges at VDD/2
250
ps
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Duty cycle on outputs will match incoming clock duty cycle. Consult ICS for tight duty cycle clock generators.
3. With external series resistor of 33 W positioned close to each output pin.
MDS 551 B
3
Revision 091200
Printed 11/14/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
PRELIMINARY INFORMATION
ICS551
1 to 4 Clock Buffer
Package Outline and Package Dimensions
8 pin SOIC
E
H
Inches
Millimeters
Min Max
0.055 0.068 1.397 1.7272
Pin 1
Symbol Min
Max
A
b
0.013 0.019 0.330
0.185 0.200 4.699
0.150 0.160 3.810
0.225 0.245 5.715
0.483
5.080
4.064
6.223
D
E
H
e
h x 45°
D
.050 BSC
0.015
0.016 0.035 0.406
0.004 0.01 0.102
1.27 BSC
A
Q
h
0.381
0.889
0.254
c
L
Q
b
e
L
Ordering Information
Part/Order Number
ICS551M
Marking
ICS551M
ICS551M
Package
8 pin SOIC
8 pin SOIC on tape and reel
Temperature
0 to 70 °C
0 to 70 °C
ICS551MT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in
normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any
ICS product for use in life support devices or critical medical instruments.
ClockBlocks is a trademark of ICS
MDS 551 B
4
Revision 091200
Printed 11/14/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
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