ICS557-05A [ICSI]
Quad Differential PCI-Express Clock Source; 四路差分的PCI-Express时钟源
| 型号： | ICS557-05A |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Quad Differential PCI-Express Clock Source |
| 文件： | 总12页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS557-05A
Quad Differential PCI-Express Clock Source
Description
Features
The ICS557-05A is a spread-spectrum clock generator
that supports PCI-Express requirements. It is used in
PC or embedded systems to substantially reduce
electro-magnetic interference (EMI). The device
provides four differential HCSL or LVDS high-frequency
outputs with spread spectrum capability. The output
frequency and spread type are selectable using
external pins.
• Packaged in 20-pin TSSOP
• Available in Pb (lead) free package
• Supports PCI-Express applications
• Four differential spread spectrum clock outputs
• Spread spectrum for EMI reduction
• Uses external 25 MHz clock or crystal input
• Power down pin turns off chip
• OE control tri-states outputs
• Spread and frequency selection via external pins
• Spread Bypass option available
• Industrial temperature range available
Block Diagram
VDD
PD
OE
2
Spread
Spectrum/
Output
Spread
Spectrum
Circuitry
3
SEL[2:0]
X1
clock
selection
CLKOUTA
CLKOUTA
CLKOUTB
25 MHz
crystal or
clock
Clock
Oscillator
PLL Clock
Synthesis
CLKOUTB
CLKOUTC
X2
CLKOUTC
CLKOUTD
Optional tuning crystal
capacitors
CLKOUTD
2
Rr(IREF)
GND
MDS 557-05A E
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Revision 011606
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-05A
Quad Differential PCI-Express Clock Source
Pin Assignment
1
2
20
19
18
17
16
15
14
13
12
11
CLKA
VDDXD
S0
CLKA
S1
S2
X1
X2
PD
3
CLKB
4
CLKB
5
GNDODA
VDDODA
CLKC
6
7
OE
GNDXD
IREF
8
CLKC
9
CLKD
10
CLKD
20-pin (173 mil) TSSOP
Spread Spectrum Selection Table
Output
Frequency (MHz)
S2 S1 S0 Spread%
Spread Type
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-0.5
-1.0
-1.5
Down
Down
Down
100
100
100
100
200
200
200
200
No Spread Not Applicable
-0.5
-1.0
-1.5
Down
Down
Down
No Spread Not Applicable
MDS 557-05A E
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Revision 011606
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-05A
Quad Differential PCI-Express Clock Source
Pin Descriptions
Pin
Pin
Name
Pin
Type
Pin Description
1
2
3
4
5
6
7
8
VDDXD
S0
Power Connect to +3.3 V digital supply.
Input
Input
Input
Input
Spread spectrum select pin #0. See table above. Internal pull-up resistor.
Spread spectrum select pin #1. See table above Internal pull-up resistor.
Spread spectrum select pin #2. See table above. Internal pull-up resistor.
Crystal connection. Connect to a fundamental mode crystal or clock input.
S1
S2
X1
X2
Output Crystal connection. Connect to a fundamental mode crystal or leave open.
PD
Input
Input
Powers down all PLL’s and tri-states outputs when low. Internal pull-up resistor.
OE
Provides output on, tri-states output (High = enable outputs; Low = disable outputs).
Internal pull-up resistor.
9
GND
IREF
Power Connect to digital ground.
10
11
12
13
14
15
16
Output Precision resistor attached to this pin is connected to the internal current reference.
Output Selectable 100/200 MHz spread spectrum differential Compliment output clock D.
Output Selectable 100/200 MHz spread spectrum differential True output clock D.
Output Selectable 100/200 MHz spread spectrum differential Compliment output clock C.
Output Selectable 100/200 MHz spread spectrum differential True output clock C.
Power Connect to +3.3 V analog supply.
CLKD
CLKD
CLKC
CLKC
VDDODA
GND
Power Connect to analog ground.
17
18
19
20
CLKB
CLKB
CLKA
CLKA
Output Selectable 100/200 MHz spread spectrum differential Compliment output clock B.
Output Selectable 100/200 MHz spread spectrum differential True output clock B.
Output Selectable 100/200 MHz spread spectrum differential Compliment output clock A.
Output Selectable 100/200 MHz spread spectrum differential True output clock A.
MDS 557-05A E
3
Revision 011606
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-05A
Quad Differential PCI-Express Clock Source
Application Information
Decoupling Capacitors
Load Resistors RL
As with any high-performance mixed-signal IC, the
ICS557-05A must be isolated from system power
supply noise to perform optimally.
Since the clock outputs are open source outputs, 50
ohm external resistors to ground are to be connected at
each clock output.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-05A are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown
in detail in the PCI-Express Layout Guidelines
section.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
Each 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
bead and bulk decoupling from the device is less
critical.
The ICS557-05A can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS557-05A.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
External Components
A minimum number of external components are
required for proper operation. Decoupling capacitors of
0.01 µF should be connected between VDD and GND
pairs (1,9 and 15,16) as close to the device as possible.
On chip capacitors- Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value (in pf) of these
crystal caps equal (C -12)*2 in this equation,
L
C =crystal load capacitance in pf. For example, for a
L
crystal with a 16 pF load cap, each external crystal cap
would be 8 pF. [(16-12)x2]=8.
Current Reference Source Rr (Iref)
If board target trace impedance (Z) is 50Ω, then Rr =
475Ω (1%), providing IREF of 2.32 mA, output current
(I ) is equal to 6*IREF.
OH
MDS 557-05A E
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Revision 011606
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-05A
Quad Differential PCI-Express Clock Source
Output Structures
6*IREF
IREF
=2.3 mA
See Output Termination
Sections - Pages 3 ~ 5
Ω
RR 475
General PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1. Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible.
2. No vias should be used between decoupling
capacitor and VDD pin.
3. The PCB trace to VDD pin should be kept as short
as possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from
the device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (any ferrite beads and bulk decoupling
capacitors can be mounted on the back). Other signal
traces should be routed away from the
ICS557-05A.This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
MDS 557-05A E
5
Revision 011606
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-05A
Quad Differential PCI-Express Clock Source
PCI-Express Layout Guidelines
Common Recommendations for Differential Routing
Dimension or Value Unit
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
L3 length, Route as non-coupled 50 ohm trace.
RS
RT
0.5 max
0.2 max
0.2 max
33
inch
inch
inch
ohm
ohm
49.9
Differential Routing on a Single PCB
Dimension or Value Unit
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
2 min to 16 max
1.8 min to 14.4 max
inch
inch
Differential Routing to a PCI Express Connector
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value Unit
0.25 to 14 max inch
0.225 min to 12.6 max inch
PCI-Express Device Routing
L1
L2
L4
RS
RS
L4’
L1’
L2’
RT
RT
PCI-Express
Load or
Connector
ICS557-05A
Output
L3’ L3
Clock
Typical PCI-Express (HCSL)
Waveform
700 mV
0
500 ps
500 ps
tOR
tOF
0.52 V
0.175 V
0.52 V
0.175 V
MDS 557-05A E
6
Revision 011606
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-05A
Quad Differential PCI-Express Clock Source
LVDS Compatible Layout Guidelines
LVDS Recommendations for Differential Routing
Dimension or Value Unit
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
RP
RQ
0.5 max
0.2 max
100
100
150
inch
inch
ohm
ohm
ohm
RT
L3 length, Route as coupled 50 ohm differential trace.
L3 length, Route as coupled 50 ohm differential trace.
LVDS Device Routing
L1
L3
L3’
RQ
RP
L1’
RT
RT
ICS557-05A
Clock
LVDS
Device
Load
L2’ L2
Output
Typical LVDS Waveform
1325 mV
1000 mV
500 ps
500 ps
tOR
tOF
1250 mV
1150 mV
1250 mV
1150 mV
MDS 557-05A E
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Revision 011606
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-05A
Quad Differential PCI-Express Clock Source
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-05A. These ratings
are stress ratings only. Functional operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed
only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD, VDDA
5.5 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
0 to +70°C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
-40 to +85°C
-65 to +150°C
125°C
Junction Temperature
Soldering Temperature
260°C
ESD Protection (Input)
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85°C
Parameter
Supply Voltage
Input High Voltage
Symbol
Conditions
Min.
3.135
2.0
Typ.
Max.
3.465
VDD +0.3
0.8
Units
V
1
V
V
IH
1
Input Low Voltage
V
VSS-0.3
-5
V
IL
2
Input Leakage Current
I
0 < Vin < VDD
5
µA
mA
mA
µA
pF
pF
nH
kΩ
kΩ
IL
Operating Supply Current
I
50Ω, 2pF load@ 100MHz
OE =Low
105
40
DD
I
DDOE
I
No load, PD =Low
Input pin capacitance
Output pin capacitance
500
DDPD
Input Capacitance
Output Capacitance
Pin Inductance
C
7
6
5
IN
C
OUT
L
PIN
Output Resistance
Pull-up Resistance
Rout
CLK outputs
3.0
R
OE, SEL, PD pins
110
PUP
1 Single edge is monotonic when transitioning through region.
2 Inputs with pull-ups/-downs are not included.
MDS 557-05A E
8
Revision 011606
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-05A
Quad Differential PCI-Express Clock Source
AC Electrical Characteristics - CLKOUTA/CLKOUTB
Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature -40 to +85°C
Parameter
Input Frequency
Output Frequency
Symbol
Conditions
Min.
Typ.
Max.
Units
MHz
MHz
MHz
mV
25
HCSL termination
200
100
850
LVDS termination
1,2
Output High Voltage
V
660
-150
250
700
0
OH
1,2
Output Low Voltage
Crossing Point
V
mV
OL
Absolute
350
550
140
mV
1,2
Voltage
Crossing Point
Variation over all edges
mV
1,2,4
Voltage
1,3
Jitter, Cycle-to-Cycle
60
ps
kHz
ps
Modulation Frequency
Spread spectrum
30
31.5
332
344
33
700
700
50
1,2
Rise Time
t
From 0.175 V to 0.525 V
From 0.525 V to 0.175 V
At crossing point Voltage
175
175
OR
1,2
Fall Time
t
ps
OF
Skew between outputs
ps
1,3
Duty Cycle
45
55
%
5
Output Enable Time
All outputs
10
us
5
Output Disable Time
All outputs
10
us
Power-up Time
t
From power-up VDD=3.3 V
Settling period after spread change
3.0
3.0
ms
ms
STABLE
Spread Change Time
t
SPREAD
1
Test setup is R =50 ohms with 2 pF, Rr = 475Ω (1%).
L
2
3
4
5
Measurement taken from a single-ended waveform.
Measurement taken from a differential waveform.
Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.
CLKOUT pins are tri-stated when OE is low. asserted. CLKOUT is driven differential when OE is high unless its
PD= low.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
Still air
93
78
65
20
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
θ
MDS 557-05A E
9
Revision 011606
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-05A
Quad Differential PCI-Express Clock Source
PCI-Express Layout Guidelines
Common Recommendations for Differential Routing
Dimension or Value Unit
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
L3 length, Route as non-coupled 50 ohm trace.
RS
RT
0.5 max
0.2 max
0.2 max
33
inch
inch
inch
ohm
ohm
49.9
Differential Routing on a Single PCB
Dimension or Value Unit
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
2 min to 16 max
1.8 min to 14.4 max
inch
inch
Differential Routing to a PCI Express Connector
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value Unit
0.25 to 14 max inch
0.225 min to 12.6 max inch
PCI-Express Device Routing
L1
L2
L4
RS
RS
L4’
L1’
L2’
RT
RT
PCI-Express
Load or
Connector
ICS557-03
Output
L3’ L3
Clock
Typical PCI-Express (HCSL) Waveform
700 mV
0
500 ps
500 ps
tOR
tOF
0.52 V
0.175 V
0.52 V
0.175 V
MDS 557-05A E
10
Revision 011606
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-05A
Quad Differential PCI-Express Clock Source
Package Outline and Package Dimensions (20-pin TSSOP, 173 mil Body)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Millimeters
Inches*
20
Symbol
Min
Max
1.20
0.15
1.05
0.30
0.20
6.60
Min
Max
A
A1
A2
b
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
6.40
6.40 BASIC
4.30 4.50
0.65 Basic
0.002
0.032
0.007
E1
E
INDEX
AREA
c
D
E
0.0035 0.008
0.252 0.260
0.252 BASIC
0.169 0.177
0.0256 Basic
E1
e
1
2
D
L
0.45
0°
0.75
8°
0.018
0°
0.030
8°
α
aaa
--
0.10
--
0.004
*For reference only. Controlling dimensions in mm.
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
aaa C
MDS 557-05A E
11
Revision 011606
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-05A
Quad Differential PCI-Express Clock Source
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Tubes
Package
Temperature
0 to +70°C
ICS557G-05A
ICS557G-05ATR
ICS557G-05ALF
ICS557G-05ALFTR
ICS557GI-05A
ICS557G-05A
ICS557G-05A
557G-05ALF
557G-05ALF
557GI-05A
20-pin TSSOP
20-pin TSSOP
20-pin TSSOP
20-pin TSSOP
20-pin TSSOP
20-pin TSSOP
20-pin TSSOP
20-pin TSSOP
Tape and Reel
Tubes
0 to +70°C
0 to +70°C
Tape and Reel
Tubes
0 to +70°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
ICS557GI-05ATR
ICS557GI-05ALF
ICS557GI-05ALFTR
557GI-05A
Tape and Reel
Tubes
557GI05ALF
557GI05ALF
Tape and Reel
Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 557-05A E
12
Revision 011606
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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