ICS558G-01LF [ICSI]

PECL/CMOS TO CMOS CLOCK DIVIDER; PECL / CMOS和CMOS时钟分频器


型号：	ICS558G-01LF
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	PECL/CMOS TO CMOS CLOCK DIVIDER PECL / CMOS和CMOS时钟分频器逻辑集成电路光电二极管驱动时钟
文件：	总5页 (文件大小：132K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS558-01

PECL/CMOS TO CMOS CLOCK DIVIDER

Description

Features

The ICS558-01 accepts a high speed input of either

• 16-pin TSSOP package

PECL or CMOS, integrates a divider of 1, 2, 3, or 4, and

provides four CMOS low skew outputs. The chip also

has output enables so that one, three, or all four

outputs can be tri-stated.

• Available in Pb (lead) free package

• Selectable PECL or CMOS inputs

• Operates up to 250 MHz

• Works as a voltage translator

• Four low skew (<250 ps) outputs

The ICS558-01 is a member of the ICS Clock Blocks™

family of clock generation, synchronization, and

distribution devices.

• Selectable internal divider

• Operating input voltages of 3.3 V or 5.0 V

• Operating output voltages of 2.5 V, 3.3 V or 5.0 V

• Ideal for IA64 designs

Block Diagram

VDDP

VDDC

OE0

PECLIN

CLK1

CLK2

Output Divide

CMOSIN

SELPECL

S0, S1

CLK3

CLK4

OE1

GND

MDS 558-01 C

Revision 122105

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

ICS558-01

PECL/CMOS TO CMOS CLOCK DIVIDER

Input Clock Selection

Pin Assignment

SELPECL

Input

SELPECL

VDDC

CLK1

CLK2

CLK3

CLK4

GND

CMOSIN

PECLIN

VDDP

PECLIN

GND

Tri-State Table

OE1 OE0

CLK 1

Tri-state

Clock ON

Tri-state

Clock ON

CLK 2, 3, 4

Tri-state

CMOSIN

OE0

Tri-state

OE1

Clock ON

16-pin 173 Mil (0.65mm) TSSOP

Output Divide Selection

Output Divide

Pin Descriptions

Pin Type

Pin Description

Number

Name

Input

Select 0 for output divider. See table above. Internal pull-up to VDDP.

Select 1 for output divider. See table above. Internal pull-up to VDDP.

Connect to +3.3 V or +5 V. Decouple to pin 6.

PECL input. Connect to ground if not used.

Complimentary PECL input. Connect to ground if not used.

Connect to ground.

VDDP

PECLIN

GND

Power

Clock Input

Power

CMOSIN

OE0

Clock Input

Input

CMOS input. Connect to ground if not used.

Output Enable 0. See table above. Internal pull-up to VDDP.

Output Enable 1. See table above. Internal pull-up to VDDP.

Connect to ground.

OE1

Input

GND

Power

CLK4

CLK3

CLK2

CLK1

VDDC

SELPECL

Output

Power

Low skew clock output.

Connect to +2.5 V, +3.3 V, or +5 V. Decouple to pin 10.

Input

Selects PECL or CMOS input. See table above. Internal pull-up to

VDDP.

MDS 558-01 C

Revision 122105

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

ICS558-01

PECL/CMOS TO CMOS CLOCK DIVIDER

External Components

The ICS558-01 requires two 0.01 µF capacitors between VDDP and GND, and VDDC and GND—one on

each side of the chip. These must be close to the chip to minimize lead inductance. Series termination

resistors of 33Ω can be used on the outputs (these also must be close to the chip).

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the ICS558-01. These ratings,

which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of

the device at these or any other conditions above those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can

affect product reliability. Electrical parameters are guaranteed only over the recommended operating

temperature range.

Item

Rating

Supply Voltage; VDDP, VDDC (referenced to ground)

Inputs and Clock Outputs (referenced to ground)

Ambient Operating Temperature

7.0 V

-0.5 V to VDD+0.5 V

0 to +70 °C

Storage Temperature

-65 to +150 °C

260 °C

Soldering Temperature (maximum of 10 seconds)

DC Electrical Characteristics

VDDP = VDDC = 3.3V (unless stated otherwise), Ambient temperature 0 to +70 °C

Parameter

Symbol

Conditions

VDDP ≥ VDDC

Min.

3.0

Typ.

Max.

5.5

Units

Operating Voltage, VDDP

Operating Voltage, VDDC

Input High Voltage, CMOSIN

Input Low Voltage, CMOSIN

Input High Voltage

2.375

VDDP

(VDDP/2)+1

(VDDP/2)-1

VDDP

non-clock pins

VDDP=5 V

VDDP-0.5

Input Low Voltage

0.5

Common Mode Range,

PECLIN

VDDP-3.7

VDDP-2.0

0.3

VDDP-0.6

Common Mode Range,

PECLIN

VDDP=3.3 V

VDDP-0.6

1.0

Peak-to-Peak Input Voltage,

PECLIN

Output High Voltage

Output Low Voltage

Output High Voltage

VDDC = 5 V,

VDDC-0.4

= -24 mA

VDDC = 5 V,

= 24 mA

0.4

VDDC = 3.3 V,

= -18 mA

VDDC-0.4

MDS 558-01 C

Revision 122105

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

ICS558-01

PECL/CMOS TO CMOS CLOCK DIVIDER

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Output Low Voltage

VDDC = 3.3 V,

0.4

= 18 mA

Output High Voltage

VDDC = 2.5 V,

= -8 mA

VDDC-0.4

Output Low Voltage

VDDC = 2.5 V

= 8 mA

0.4

Operating Supply Current

IDDP

IDDC

No load, 100

MHz input

No load, 100

MHz input

Short Circuit Current

On-chip pull-up resistor

Input Capacitance

+70

250

kΩ

AC Electrical Characteristics

VDDP = VDDC = 3.3 V (unless stated otherwise), Ambient Temperature 0 to +70 °C

Parameter

Symbol

Conditions

Min.

Typ. Max. Units

Input Frequency

250

800

750

250

MHz

Output Rise Time

Output Fall Time

Skew, between any output

clocks

(Assumes identically

loaded outputs with

identical rise times,

measured at VDDC/2)

Propagation Delay

5.0

6.0

7.0

Output Clock Duty Cycle for /2

and /4

Output Clock Duty Cycle for /1

and /3

Thermal Characteristics (16-pin TSSOP)

Parameter

Symbol

Conditions

Min.

Typ. Max. Units

Thermal Resistance Junction to

Ambient

Still air

°C/W

1 m/s air flow

3 m/s air flow

Thermal Resistance Junction to Case

MDS 558-01 C

Revision 122105

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

ICS558-01

PECL/CMOS TO CMOS CLOCK DIVIDER

Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)

Package dimensions are kept current with JEDEC Publication No. 95, MO-153

Millimeters

Min Max

Inches

Max

Symbol

Min

1.20

0.15

1.05

0.30

0.20

5.1

0.047

0.006

0.041

0.012

0.05

0.80

0.19

0.09

4.90

0.002

0.032

0.007

INDEX

AREA

0.0035 0.008

0.193 0.201

0.252 BASIC

0.169 0.177

0.0256 Basic

6.40 BASIC

4.30 4.50

0.65 Basic

0.45

0°

0.75

8°

0.018

0°

0.030

8°

aaa

0.10

0.004

- C -

SEATING

PLANE

aaa C

Ordering Information

Part / Order Number

Marking

Shipping Packaging

Tubes

Package

Temperature

0 to +70°C

ICS558G-01

ICS558G-01T

ICS558G-01LF

ICS558G-01LFT

ICS558G-01

558G-01LF

16-pin TSSOP

Tape and Reel

Tubes

Tape and Reel

Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)

assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would

result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial

applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary

environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any

circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or

critical medical instruments.

MDS 558-01 C

Revision 122105

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

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