ICS601G-21 [ICSI]
LOW PHASE NOISE CLOCK MULTIPLIER; 低相位噪声时钟乘法器
| 型号： | ICS601G-21 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW PHASE NOISE CLOCK MULTIPLIER |
| 文件： | 总6页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS601-21
LOW PHASE NOISE CLOCK MULTIPLIER
Description
Features
The ICS601-21 is a low-cost, low phase noise, high
performance clock synthesizer for applications which
require low phase noise and low jitter. It is ICS’ lowest
phase noise multiplier. Using ICS’ patented analog and
digital Phase Locked Loop (PLL) techniques, the chip
accepts a 10 - 27 MHz crystal or clock input, and
produces output clocks up to 220 MHz at 3.3 V.
• Fully integrated PLL, no external loop filter required
• Differential 3.3 V LVPECL outputs
• Uses fundamental 10 - 27 MHz crystal or clock
• Output clocks up to 220 MHz at 3.3 V
• Low phase noise: -122 dBc/Hz at 10 kHz
• Low jitter - 15 ps one sigma typ.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
• Powerdown mode lowers power consumption
• Packaged in 16-pin TSSOP
• Advanced, low power, sub-micron CMOS process
• Operating voltage of 3.3 V
• Commercial temperature range available
Block Diagram
VDD
Reference
Divider
Charge
Pump
Loop
Filter
Phase
Comparator
VCO
CLK
nCLK
X1/ICLK
X2
VCO
Divide
Crystal or
clock input
Crystal
Oscillator
ROM Based
Multipliers
4
S2:0
GND
MDS 601-21 H
1
Revision 040204
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS601-21
LOW PHASE NOISE CLOCK MULTIPLIER
Pin Assignment
Multiplier Select Table
S2
0
S1
0
S0
0
Multiplier
X1
VDD
VDD
VDD
GND
VDD
GND
GND
1
2
3
4
5
6
7
8
X2
16
15
14
13
12
11
10
9
x1
x2
x3
x4
x5
x6
x8
x16
GND
CLK
nCLK
VDD
S0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
S1
1
1
0
S2
1
1
1
16 Pin (173 mil) TSSOP
0 = connect directly to ground
1 = connect directly to VDD
Pin Descriptions
Pin
Pin
Pin
Pin Description
Number
Name
Type
1
X1
XI
Crystal or clock input. Connect to a 10-27 MHz fundamental parallel mode
crystal or clock input.
2 - 4
5
VDD
GND
VDD
GND
S2
Power Connect to +3.3 V.
Power Connect to ground.
Power Connect to +3.3 V.
Power Connect to ground.
6
7 - 8
9
Input
Input
Input
Select pin 2. Internal pull-up resistor.
10
11
12
13
14
15
16
S1
Select pin 1. Internal pull-up resistor.
Select pin 0. Internal pull-up resistor.
S0
VDD
nCLK
CLK
GND
X2
Power Connect to +3.3 V.
Output Inverted differential clock output.
Output Differential clock output.
Power Connect to ground.
XO
Crystal connection. Connect to 10-27MHz fundamental parallel mode crystal
or leave unconnected for clock input.
MDS 601-21 H
2
Revision 040204
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS601-21
LOW PHASE NOISE CLOCK MULTIPLIER
External Components
The ICS601-21 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01 µF and 0.1 µF should be connected between VDD and GND, as close to the part as
possible. A 50 Ω terminating resistor should be used on each clock output. (See termination diagram on
page 5). The crystal must be connected as close to the chip as possible. The crystal should be
fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal,
capacitors should be connected from pins X1 to ground and X2 to ground. In general, the value of these
capacitors is given by the following equation, where CL is the crystal load capacitance: Crystal caps (pF) =
(CL-5) x 2. So for a crystal with 16 pF load capacitance, two 22 pF caps can be used. For any given board
layout, ICS can measure the board capacitance and recommend the exact capacitance value to use.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS601-21. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70 °C
-65 to +150 °C
125 °C
Ambient Operating Temperature, Commercial version
Storage Temperature
Junction Temperature
Soldering Temperature
260 °C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
+3.0
+3.6
V
DC Electrical Characteristics
VDD=3.3 V 10%, Ambient temperature 0 to +70°C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.0
3.6
V
V
V
Input High Voltage
Input Low Voltage
V
X1/ICLK pin only VDD/2+1
X1/ICLK pin only
IH
V
VDD/2-1
IL
MDS 601-21 H
3
Revision 040204
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS601-21
LOW PHASE NOISE CLOCK MULTIPLIER
DC Electrical Characteristics (continued)
Parameter
Input High Voltage
Symbol
Conditions
Input select pins
Input select pins
Note 1
Min.
Typ.
Max.
VDD
Units
V
V
2
IH
Input Low Voltage
V
0.8
V
IL
Output High Voltage
Output Low Voltage
Output Voltage Swing
Operating Supply Current
Input Capacitance
V
VDD-1.4
VDD-2.0
0.6
VDD-1.0
VDD-1.7
0.95
V
OH
V
Note 1
V
OL
V
Peak to Peak
Note 1, 125 MHz
Input select pins
Input select pins
V
swing
IDD
30
5
45
mA
pF
kΩ
C
IN
On Chip Pull-up Resistor
R
510
PU
Note 1: Outputs terminated with 50Ω to VDD-2V
AC Electrical Characteristics
VDD = 3.3 V 10%, Ambient Temperature 0 to +70° C
Parameter
Crystal Input Frequency
Output Frequency
Symbol
Conditions
Min. Typ. Max.
Units
MHz
MHz
ps
Fin
Note 2
10
10
27
220
900
1200
55
Output Rise Time
t
20% to 80%, no load
80% to 20%, no load
at VDD/2
600
900
50
OR
Output Fall Time
t
ps
OF
Output Clock Duty Cycle
45
%
Maximum Absolute Jitter, short
term, 125 MHz
No load
50
75
ps
Maximum Jitter, one sigma,
125 MHz (x5)
No load
12
20
ps
Phase Noise, relative to carrier,
125 MHz (x5)
100 Hz offset
1 kHz
-90
-94
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
-116
-118
-115
-120
-122
-119
Phase Noise, relative to carrier,
125 MHz (x5)
10 kHz offset
100 kHz offset
Phase Noise, relative to carrier,
125 MHz (x5)
Note 2: Input frequency limited by maximum output frequency and multiplication factor (I.e. For 16x,
maximum input frequency is 13.75 MHz).
MDS 601-21 H
4
Revision 040204
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS601-21
LOW PHASE NOISE CLOCK MULTIPLIER
Parameter Measurement Information
VD D = 3.3V
VD D = 3.3V
SCOPE
Z = 50Ω
Z = 50Ω
Z = 50Ω
Qx
Qx
50Ω
LVPECL
LVPECL
Z = 50Ω
nQx
nQx
50Ω
50Ω
50Ω
GND =0V
GND =0V
VD D-2V = 1.3V
3.3V Output Load AC Test Circuit
3.3V LVPECL Driver Termination
VOH
nFOUT
VREF
VOL
FOUT
Reference Point
tcycle(n)
tcycle(n+1)
HISTOGRAM
Mean Period
(First edge after trigger)
tjit(cc) = tcycle(n) - tcycle(n+1)
1000 Cycles
1s contains 68.26% of all measurements
2s contains 95.4% of all measurements
3s contains 99.73% of all measurements
4s contains 99.99366% of all measurements
6s contains (100-1.973x10-7)% of all measurements
Period Jitter
CYCLE-TO-CYCLE JITTER
nFOUT
FOUT
80%
80%
VSWING
20%
20%
Pulse Width
Clock
Outputs
tPERIOD
tOR
tOF
tPW
ODC =
tPERIOD
OUTPUT DUTY CYCLE AND tPERIOD
OUTPUT RISE/FALL TIME
MDS 601-21 H
5
Revision 040204
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS601-21
LOW PHASE NOISE CLOCK MULTIPLIER
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Min Max
Inches
Max
16
Symbol
Min
--
A
A1
A2
b
C
D
E
E1
e
L
α
--
1.20
0.15
1.05
0.30
0.20
5.1
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E1
E
INDEX
AREA
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
6.40 BASIC
4.30 4.50
0.65 Basic
1
2
D
0.45
0°
0.75
8°
0.018
0°
0.030
8°
aaa
--
0.10
--
0.004
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
Marking
Shipping
packaging
Package
Temperature
ICS601G-21
ICS601G-21
ICS601G-21
Tubes
16-pin TSSOP
16-pin TSSOP
0 to 70° C
0 to 70° C
ICS601G-21T
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other
circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those
requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant
any ICS product for use in life support devices or critical medical instruments.
MDS 601-21 H
6
Revision 040204
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
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