ICS613MLF [ICSI]
LOW PHASE NOISE CLOCK MULTIPLIER; 低相位噪声时钟乘法器
| 型号： | ICS613MLF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW PHASE NOISE CLOCK MULTIPLIER |
| 文件： | 总6页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS613
LOW PHASE NOISE CLOCK MULTIPLIER
Description
Features
The ICS613 is a low cost, low phase noise, high
• Packaged in 16 pin SOIC
performance clock synthesizer for any applications that
require low phase noise and low jitter. It is ICS’ lowest
phase noise multiplier. Using ICS’ patented analog and
digital Phase Locked Loop (PLL) techniques, the chip
can accept a 25MHz crystal or clock input, and
produces output clocks up to 157.5 MHz.
• Available in Pb (lead) free package
• Uses a fundamental 25MHz crystal or clock
• Operating voltage of 3.3 V
• Separate output voltage supplies which can run at
2.5 V or 3.3 V
The chip has separate power supplies for the clock
outputs, allowing each output to be run at different
voltages. It also allows the core of the chip to operate at
3.3V, while the output clocks run at either 2.5V or 3.3V.
• Output clocks up to 157.5 MHz
• Low phase noise: -110 dBc/Hz at 10 kHz
• Low jitter of 36 ps (one sigma)
• Advanced, low power, sub-micron CMOS process
Block Diagram
VDDO1
2
VDD
Phase
Comparator,
X1/ICLK
VCO
CLK1
CLK2
Charge Pump,
and Loop Filter
Reference
Divider
Crystal
Oscillator
Output
Divider
Crystal or
clock input
X2
VCO
Divider
Capacitors must be used
with a crystal input
5
GND
3
VDDO2
S2:SO
MDS 613 C
1
Revision 111204
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS613
LOW PHASE NOISE CLOCK MULTIPLIER
Pin Assignment
Clock Select Table
S2 S1 S0
Input
Output (CLK1
and CLK2)
X1/ICLK
S0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
25
25
25
25
25
25
25
25
125
156.25
143.75
150
S1
S2
GND
VDD
GND
VDDO1
CLK1
GND
VDD
GND
VDDO2
CLK2
GND
146.875
157.5
140
156.25
16 Pin (150 mil) SOIC
Pin Descriptions
Pin
Number
Pin
Name
Pin
Pin Description
Type
Input
Input
Input
1
2
XI/ICLK
S0
Crystal Connection. Connect to a 25 MHz crystal or clock.
Select pin 0. Internal pull-down.
3
S2
Select pin 2. Internal pull-down.
4
VDD
GND
VDDO2
CLK2
GND
GND
CLK1
VDDO1
GND
VDD
GND
S1
Power Connect to +3.3V. Must be the same as pin 13.
Power Connect to ground.
5
6
Power Output VDD for CLK2. Connect to either +2.5V or +3.3V.
Output CLK2 output. Frequency based on table above.
Power Connect to ground.
7
8
9
Power Connect to ground.
10
11
12
13
14
15
16
Output CLK1 output. Frequency based on table above.
Power Output VDD for CLK1. Connect to either +2.5V or +3.3V.
Power Connect to ground.
Power Connect to +3.3V. Must be the same as pin 4.
Power Conenct to ground.
Input
Input
Select pin 1. Internal pull-up.
X2
Crystal Connection. Connect to a 25 MHz crystal. Leave
unconnected for clock input.
MDS 613 C
2
Revision 111204
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS613
LOW PHASE NOISE CLOCK MULTIPLIER
External Component Selection
The ICS613 requires a minimum number of external
components for proper operation.
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal
Decoupling Capacitors
Decoupling capacitors of 0.01µF should be connected
between VDD and GND pairs on pins 4 and 5, pins 6
and 8, pins 11 and 9, and pins 13 and 14 as close to
the ICS613 as possible. For optimum device
performance, the decoupling capacitors should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
(C -6pF)*2. In this equation, C = crystal load
L
L
capacitance in pF.
Example: For a crystal with a 16 pF load capacitance,
each crystal capacitor would be 20 pF [(16-6) x 2] = 20.
Series Termination Resistor
When the PCB traces between the clock outputs and
the loads are over 1 inch, series termination should be
used. To series terminate a 50Ω trace (a commonly
used trace impedance) place a 33Ω resistor in series
with the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20Ω.
Reducing Jitter and Phase Noise
For applications that only require one output, jitter and
phase noise can be reduced by tying the unused
VDDO to ground. This will stop the output clock low
which will result in less switching noise on the active
output.
Crystal Tuning Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS613. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7V
-0.5V to VDD+0.5V
0 to +70°C
Ambient Operating Temperature
Storage Temperature
-65 to +150°C
260°C
Soldering Temperature
MDS 613 C
3
Revision 111204
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS613
LOW PHASE NOISE CLOCK MULTIPLIER
Recommended Operation Conditions
Parameter
Min.
0
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
–
+3.15
+3.45
V
DC Electrical Characteristics
VDD=3.3V ±±5 , Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Symbol
VDD
Conditions
Min.
3.15
2.375
2.4
Typ.
Max.
Units
Operating Voltage
3.45
VDD
V
V
V
V
V
Output Voltage
VDDO
Output High Voltage
Output Low Voltage
V
I
I
I
= -12 mA
= 12 mA
= -4 mA
OH
OH
OL
OH
V
0.4
OL
Output High Voltage (CMOS
Level)
V
VDD-0.4
2.5
OH
Input High Voltage (S2:S0)
Input Low Voltage (S2:S0)
Operating Supply Current
Short Circuit Current
V
V
V
IH
V
0.5
IL
IDD
No load
27
50
mA
mA
I
OS
AC Electrical Characteristics
VDD = 3.3V ±±5, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Input Frequency
f
25
MHz
MHz
ps
in
Output Frequency
Output Rise Time
f
125
157.5
out
OR
t
20% to 80%, C =15pF,
VDD=3.3V
700
700
L
Output Fall Time
t
80% to 20%, C =15pF,
ps
ns
ns
%
OF
L
VDD=3.3V
Output Rise Time
Output Fall Time
t
20% to 80%, C =15pF,
1.0
1.0
55
OR
L
VDDO’s=2.5V
t
80% to 20%, C =15pF,
OF
L
VDDO’s=2.5V
Output Clock Duty Cycle
t
At VDDO’s/2, C =15pF
45
50
D
L
MDS 613 C
4
Revision 111204
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS613
LOW PHASE NOISE CLOCK MULTIPLIER
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Maximum Output Jitter,
short term
t
C =15pF, 125MHz output
30
60
ps
J
L
Maximum one sigma jitter
t
C =15pF, 125MHz output
8
20
ps
SJ
L
Phase Noise, relative to
carrier, 125 MHz
100 Hz offset
-90
dBc/Hz
Phase Noise, relative to
carrier, 125 MHz
1 kHz offset
-115
-120
-115
0
dBc/Hz
dBc/Hz
dBc/Hz
ps
Phase Noise, relative to
carrier, 125 MHz
10 kHz offset
100 kHz offset
VDDO1=VDDO2
Phase Noise, relative to
carrier, 125 MHz
Skew
250
MDS 613 C
5
Revision 111204
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS613
LOW PHASE NOISE CLOCK MULTIPLIER
Package Outline and Package Dimensions (16 pin SOIC, 1±0 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
16
Symbol
Min
Max
1.75
0.25
0.51
0.25
10.00
4.00
Min
Max
A
A1
B
C
D
E
e
1.35
0.10
0.33
0.19
9.80
3.80
.0532
.0040
.013
.0075
.3859
.1497
.0688
.0098
.020
.0098
.3937
.1574
E
H
INDEX
AREA
1.27 BASIC
0.050 BASIC
1
2
H
h
L
5.80
0.25
0.40
0°
6.20
.2284
.010
.016
0°
.2440
.020
.050
8°
0.50
1.27
8°
D
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
ICS613M
Marking
ICS613M
ICS613M
ICS613MLF
ICS613MLF
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
16 pin SOIC
16 pin SOIC
16 pin SOIC
16 pin SOIC
ICS613MT
ICS613MLF
ICS613MLFT
Tape and Reel
Tubes
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 613 C
6
Revision 111204
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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