ICS650G-36 [ICSI]
Networking & PCI Clock Source; 网络和PCI时钟源
| 型号： | ICS650G-36 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Networking & PCI Clock Source |
| 文件： | 总7页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS650-36
Networking & PCI Clock Source
Description
Features
The ICS650-36 is a low cost frequency generator
designed to support networking and PCI applications.
Using analog/digital Phase Locked-Loop (PLL)
techniques, the device uses a standard fundamental
mode, inexpensive crystal input of 25 MHz to produce
four output clocks supporting LAN, PCI, and 100M
SDRAM functions.
• Packaged in 16-pin TSSOP
• Available in Pb (lead) free package
• Replaces multiple crystals and oscillators
• Input crystal or clock frequency of 25 MHz
• Fixed reference output frequency of 25 MHz
• Selectable output frequencies of 33.3, 33.333, 50,
66.666, 100, and 125 MHz
The device also has a power down feature that
tri-states the clock outputs and turns off the PLL when
the PDTS pin is taken low.
• Duty cycle of 40/60
• Operating voltage of 3.3 V
• Advanced, low-power CMOS process
• Industrial and commercial temperature ranges
Block Diagram
VDD
3
Select/
3
Control
Circuit
PLL1
PLL2
CLK1
CLK2
S2:0
PLL3
CLK3
REF
X1/ICLK
Crystal
Oscillator/
Clock
25 MHz
crystal
input
Buffer
X2
3
GND
External capacitors
may be required.
PDTS (all outputs and PLLs)
MDS 650-36 D
1
Revision 030206
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
ICS650-36
Networking & PCI Clock Source
Pin Assignment
CLK Output Selection Table
S2
0
S1
0
S0
0
REF
OFF
ON
ON
ON
ON
ON
ON
ON
CLK1
33.30
CLK2
50
CLK3
125
125
125
125
125
100
100
125
X2
X1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
GND
REF
S0
0
0
1
33.333
33.333
66.666
33.333
33.333
33.333
33.30
33.333
66.666
66.666
50
0
1
0
GND
CLK3
PDTS
S2
0
1
1
1
0
0
VDD
CLK1
GND
S1
1
0
1
50
1
1
0
66.666
50
CLK2
1
1
1
VDD
Note: All frequencies are in MHz.
16-pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X2
Output Crystal connection. Connect to 25 MHz crystal input or float for
clock.
2
3
4
X1
Input
Crystal connection. Connect to 25 MHz crystal or clock input.
GND
CLK3
Power Connect to ground.
Output Selectable clock output. See table above for frequency. Weak
internal pull-down when tri-state.
5
6
7
Powers down entire chip and tri-states outputs when low. Internal
pull-up resistor.
PDTS
S2
Input
Input
Select pin. Selects clock output frequency from table above.
Internal pull-up resistor.
CLK2
Output Selectable clock output. See table above for frequency. Weak
internal pull-down when tri-state.
8
9
VDD
S1
Power Connect to +3.3 V.
Input
Select pin. Selects clock output frequency from table above.
Internal pull-up resistor.
10
11
GND
Power Connect to ground.
CLK1
Output Selectable clock output. See table above for frequency. Weak
internal pull-down when tri-state.
12
13
VDD
S0
Power Connect to +3.3 V.
Input
Select pin. Selects clock output frequency from table above.
Internal pull-up resistor.
MDS 650-36 D
2
Revision 030206
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
ICS650-36
Networking & PCI Clock Source
Pin
Number
Pin
Name
Pin
Type
Pin Description
14
REF
Output Reference 25 MHz clock output. Weak internal pull-down when
tri-state.
15
16
GND
VDD
Power Connect to ground.
Power Connect to +3.3 V.
External Components
The value (in pF) of these crystal caps should equal
Decoupling Capacitor
(C -6 pF)*2. In this equation, C = crystal load
L
L
As with any high performance mixed-signal IC, the
ICS650-36 must be isolated from system power supply
noise to perform optimally.
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2 = 20].
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
PCB Layout Recommendations
Observed the following guidelines for optimum device
performance and lowest output phase noise:
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
Crystal Load Capacitors
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors
must be connected from each of the pins X1 and X2 to
ground.
3) Place the 33Ω series termination resistor (if needed)
close to the clock output to minimize EMI.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS650-36. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
MDS 650-36 D
3
Revision 030206
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
ICS650-36
Networking & PCI Clock Source
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-36. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
-0.5 V to 7 V
-0.5 V to VDD+0.5 V
0 to +70°C
-40 to +85°C
-65 to +150°C
125°C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
0
-40
+85
°C
+3.135
+3.3
+3.465
V
MDS 650-36 D
4
Revision 030206
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
ICS650-36
Networking & PCI Clock Source
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85°C
Parameter
Symbol
VDD
Conditions
Min.
Typ.
3.3
Max. Units
Operating Voltage
3.135
3.465
V
mA
µA
V
Supply Current
IDD
No load, PDTS=1
25
Power Down Current
Input High Voltage
IDDPD No load, PDTS=0
100
V
PDTS, S2:0
PDTS, S2:0
2
IH
Input Low Voltage
V
0.8
0.4
V
IL
Output High Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
Input Capacitance, inputs
Nominal Output Impedance
Internal Pull-up Resistor
Internal Pull-down Resistor
V
V
I
I
I
= -4 mA
= -12 mA
= 12 mA
VDD-0.3
2.4
V
OH
OH
OH
OH
OL
V
V
V
OL
OS
I
Clock outputs
65
5
mA
pF
Ω
C
IN
Z
20
OUT
R
PDTS, S2:0
Outputs
500
250
kΩ
kΩ
PU
R
PD
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85°C
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Input Frequency
f
25
0.8
0.7
MHz
ns
IN
Output Rise Time
t
20% to 80%, Note 1
80% to 20%, Note 1
at VDD/2, Note 1
Note 1
OR
Output Fall Time
t
ns
OF
Output Clock Duty Cycle
Absolute Clock Period Jitter
Clock Jitter, Cycle-to-Cycle
40
60
%
125
150
ps
33.333M, 66.666M,
Note 1
ps
Clock Jitter, Long Term
Frequency Synthesis Error
Output Enable Time
25M, n=1000, Note1
900
0
ps
ppm
µs
t
t
PDTS high to output
locked to 1%
350
OE
Output Disable Time
PDTS low to tri-state
25
ns
OD
Note 1: Measured with a 15 pF load.
MDS 650-36 D
5
Revision 030206
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
ICS650-36
Networking & PCI Clock Source
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
78
70
68
37
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
Marking Diagrams
(ICS650G-36)
(ICS650G-36LF)
16
9
16
9
650G-36
######
YYWW$$
650G36LF
######
YYWW
8
1
1
8
(ICS650GI-36)
(ICS650GI-36LF)
16
9
16
9
650GI-36
######
YYWW$$
650GI36L
######
YYWW
8
1
8
1
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. “LF” or “L” designates Pb free packaging.
4. “I” designates industrial temperature range.
5. Bottom marking: (origin). Origin = country of origin if not USA.
MDS 650-36 D
6
Revision 030206
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
ICS650-36
Networking & PCI Clock Source
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches*
16
Symbol
Min Max
Min
Max
A
A1
A2
b
--
1.20
0.15
1.05
0.30
0.20
5.1
--
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
6.40 BASIC
4.30 4.50
0.65 Basic
0.002
0.032
0.007
E1
E
INDEX
AREA
C
D
E
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
1
2
E1
e
L
D
0.45
0°
0.75
8°
0.018
0°
0.030
8°
α
aaa
--
0.10
--
0.004
*For reference only. Controlling dimensions in mm.
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa
C
Ordering Information
Part / Order Number
ICS650G-36
Marking
Shipping Packaging
Tubes
Package
Temperature
0 to +70 °C
0 to +70 °C
0 to +70 °C
0 to +70 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
ICS650G-36T
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
(see page 6)
(see page 6)
ICS650G-36LF
ICS650G-36LFT
ICS650GI-36
ICS650GI-36T
ICS650GI-36LF
ICS650GI-36LFT
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 650-36 D
7
Revision 030206
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
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