ICS671M-06IT [ICSI]
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER; 3.3伏零延迟，低偏移缓冲器
| 型号： | ICS671M-06IT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| 文件： | 总6页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS671-06
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
Description
Features
The ICS671-06 is a low phase noise, high-speed
PLL-based, 8 output, low skew zero delay buffer.
Based on ICS’ proprietary low jitter Phase-Locked
Loop (PLL) techniques, the device provides eight low
skew outputs at speeds up to 133 MHz at 3.3 V. The
outputs can be generated from the PLL (for zero delay),
or directly from the input (for testing), and can be set to
tri-state mode or to stop at a low level. For normal
operation as a zero delay buffer, any output clock is
tied to the FBIN pin.
• Clock outputs from 10 to 133 MHz
• Zero input-output delay
• Eight low skew (<200 ps) outputs
• Device-to-device skew <700 ps
• Low jitter (<200 ps)
• Full CMOS outputs with 25 mA output drive
capability at TTL levels
• 5 V tolerant FBIN and CLKIN pins
• Tri-state mode for board-level testing
• Advanced, low power, sub-micron CMOS process
• Operating voltage of 3.3 V
ICS manufactures the largest variety of clock
generators and buffers and is the largest clock supplier
in the world.
• Industrial temperature range available
• Packaged in 16-pin SOIC
• Available in Pb (lead) free package
Not recommended for new designs. See the
MK2308-1H for new designs.
Block Diagram
VDD
2
Control
Logic
2
S2, S1
CLKA1
CLKA2
CLKA3
CLKIN
FBIN
CLKA4
1
Clock
Synthesis
PLL
0
CLKB1
CLKB2
CLKB3
CLKB4
2
Feedback is shown from CLKB4 for
illustration, but may come from any output.
GND
MDS 671-06 D
1
Revision 050405
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS671-06
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
Pin Assignment
CLKIN
CLKA1
CLKA2
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBIN
CLKA4
CLKA3
VDD
GND
GND
CLKB1
CLKB2
S2
CLKB4
CLKB3
S1
16 pin narrow (150 m il) SOIC
and 16pin (173m il ) TSSOP
Output Clock Mode Select Table
S2
0
S1
0
CLKA1:A4
Tri-state (note 1)
Running
CLKB1:B4
Tri-state (note 1)
Tri-state (note 1)
Running
A & B Source
PLL
PLL Status
OFF
0
1
PLL
ON
1
0
Running
CLKIN (note 2)
PLL
OFF
1
1
Running
Running
ON
Note 1. Outputs are in high impedance state.
Note 2. Buffer mode only; not zero delay between input and output.
Pin Descriptions
Pin
Pin
Pin Type
Pin Description
Number
Name
1
CLKIN
CLKA1:A4
VDD
Input
Clock input.
2 - 3, 14 - 15
Output Clock outputs A1:A4. See table above.
4
Power
Power
Power supply. Connect to 3.3 V.
Connect to ground.
5
GND
6 - 7, 10 - 11
CLKB1:B4
S2
Output Clock outputs B1:B4. See table above.
8
Input
Input
Select input 2. See table above. Internal pull-up.
Select input 1. See table above. Internal pull-up.
Connect to ground.
9
S1
12
13
16
GND
Power
Power
Input
VDD
Power supply. Connect to 3.3 V.
FBIN
Feedback input. Connect to any output under normal operation.
MDS 671-06 D
2
Revision 050405
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS671-06
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
External Components
The ICS671-06 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between VDD and GND on pins 4 and 5, and VDD and GND on
pins 13 and 12, as close to the device as possible. A series termination resistor of 33Ω may be used to
each clock output pin to reduce reflections.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS671-06. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
CLKIN and FBIN inputs
Electrostatic Discharge
7 V
-0.5 V to VDD+0.5 V
-0.5 V to 5.5 V
2000 V
Ambient Operating Temperature
Storage Temperature
-40 to +85°C
-65 to +150°C
150°C
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+85
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
-40
+3.0
+3.6
V
DC Electrical Characteristics
VDD=3.3 V ±5%, Ambient temperature -40 to +85°C, unless stated otherwis
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Input Low Current
Input High Current
Symbol
Conditions
Min.
3.0
2
Typ.
Max. Units
VDD
3.6
V
V
V
IH
V
0.8
50
V
IL
I
VIN = 0V
mA
uA
IL
I
VIN = VDD
100
IH
MDS 671-06 D
3
Revision 050405
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS671-06
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
Parameter
Output High Voltage
Output Low Voltage
Symbol
Conditions
Min.
Typ.
Max. Units
V
I
I
I
= -12 mA
2.4
V
OH
OH
OL
OH
V
= 12 mA
= -12 mA
0.4
35
V
V
OL
Output High Voltage,
CMOS level
V
VDD-0.4
OH
Operating Supply Current
IDD
IDD
No Load, S2 = 1, S1 = 1,
Note 1
mA
Power Down Supply
Current
CLKIN = 0, S2 = 0, S1 = 1
CLKIN = 0, Note 2
Each output
12
12
±50
5
µA
µA
mA
pF
Short Circuit Current
Input Capacitance
I
OS
C
S2, S1, FBIN
IN
AC Electrical Characteristics
VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C, C
at CLK = 15 pF, unless stated otherwise
LOAD
Parameter
Symbol
Conditions
See table on page 2
See table on page 2
0.8 to 2.0 V, CL = 30 pF
2.0 to 0.8 V, CL = 30 pF
Measured at VDD/2
Min. Typ. Max. Units
Input Clock Frequency
Output Clock Frequency
Output Rise Time
f
10
10
133
133
2.5
MHz
MHz
ns
IN
t
OR
Output Fall Time
t
2.5
ns
OF
DC
Output Clock Duty Cycle
Device to Device Skew
Output to Output Skew
Input to Output Skew
t
45
50
55
%
Rising edges at VDD/2
Rising edges at VDD/2
700
200
±250
ps
ps
Rising edges at VDD/2, FBIN to
CLKA4, S1 = 1, S0 = 1, Note 1
ps
Maximum Absolute JItter
Cycle to Cycle Jitter
130
200
200
200
100
1.0
ps
ps
ps
ps
ms
30 pF, measured at 66.67M
15 pF, measured at 66.67M
15 pF, measured at 133.33M
Note 3
PLL Lock Time
Note 1: With CLKIN = 100MHz, FBIN to CLKA4, all outputs at 100 MHz.
Note 2: When there is no clock signal present at CLKIN, the ICS671-06 will enter power down mode. The
PLL is stopped and the outputs are tri-state.
Note 3: With VDD at a steady rate and valid clocks at CLKIN and FBIN.
MDS 671-06 D
4
Revision 050405
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS671-06
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
Thermal Characteristics (16 pin SOIC)
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
120
115
105
58
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
MDS 671-06 D
5
Revision 050405
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS671-06
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
16
Symbol
Min
Max
1.75
0.25
0.51
0.25
10.00
4.00
Min
Max
A
A1
B
C
D
E
e
1.35
0.10
0.33
0.19
9.80
3.80
.0532
.0040
.013
.0075
.3859
.1497
.0688
.0098
.020
.0098
.3937
.1574
E
H
INDEX
AREA
1.27 BASIC
0.050 BASIC
1
2
H
h
L
5.80
0.25
0.40
0°
6.20
.2284
.010
.016
0°
.2440
.020
.050
8°
0.50
1.27
8°
D
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Tubes
Package
Temperature
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
ICS671M-06I
ICS671M-06IT
ICS671M-06ILF
ICS671M-06ILFT
ICS671M-06I
ICS671M-06I
ICS671M-06IL
ICS671M-06IL
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
Tape and Reel
Tubes
Tape and Reel
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other
circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as
those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant
any ICS product for use in life support devices or critical medical instruments.
MDS 671-06 D
6
Revision 050405
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
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