ICS83026AMI [ICSI]
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER; 低偏移， 1到2差分至LVCMOS / LVTTL扇出缓冲器
| 型号： | ICS83026AMI |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER |
| 文件： | 总11页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83026I
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVCMOS/LVTTL FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83026I is a low skew, 1-to-2 Differ- • 2 LVCMOS / LVTTL outputs
ICS
ential-to-LVCMOS/LVTTL Fanout Buffer and a
• Differential CLK, nCLK input pair
HiPerClockS™
member of the HiPerClockS™family of High
Performance Clock Solutions from ICS.The
differential input can accept most differential sig-
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency: 350MHz (typical)
• Output skew: 20ps (maximum)
nal types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL) and
translate to two single-ended LVCMOS/LVTTL outputs with a
maximum output skew of 20ps. The small 8-lead SOIC foot-
print makes this device ideal for use in applications with lim-
ited board space.
• Part-to-part skew: 600ps (maximum)
• Small 8 lead SOIC package saves board space
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Lead-Free package available
• Pin-to-pin compatible with MC100EPT26
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nc
CLK
nCLK
nc
VDD
Q0
1
2
3
4
8
7
6
5
CLK
nCLK
Q1
Q1
GND
ICS83026I
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
TopView
83026AMI
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REV. B NOVEMBER 9, 2004
1
ICS83026I
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVCMOS/LVTTL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
nc
Type
Description
1, 4
2
Unused
Input
No connect.
CLK
nCLK
GND
Q1
Pulldown Non-inverting differential clock input.
3
Input
Pullup
Inverting differential clock input.
5
Power
Output
Output
Power
Power supply ground.
6
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
Positive supply pin.
7
Q0
8
VDD
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
VDD = 3.6V
23
pF
RPULLUP
Input Pullup Resistor
51
51
7
KΩ
KΩ
RPULLDOWN Input Pulldown Resistor
ROUT
Output Impedance
5
12
Ω
83026AMI
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REV. B NOVEMBER 9, 2004
2
ICS83026I
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVCMOS/LVTTL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
112.7°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
IDD
Power Supply Voltage
Power Supply Current
3.0
3.3
3.6
35
V
mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
2.6
V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit.
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VDD = 3.6V
Minimum Typical Maximum Units
nCLK
CLK
5
µA
µA
µA
µA
V
VIN = VDD = 3.6V
150
nCLK
CLK
VIN = 0V, VDD = 3.6V
VIN = 0V, VDD = 3.6V
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
GND + 0.5
V
DD - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
83026AMI
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REV. B NOVEMBER 9, 2004
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ICS83026I
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVCMOS/LVTTL FANOUT
BUFFER
TABLE 4. AC CHARACTERISTICS, VDD = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
350
2.1
5
MHz
ns
tPD
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
IJ 350MHz
1.7
2.5
20
tsk(o)
tsk(pp)
tR / tF
odc
ps
600
450
60
ps
0.8V to 2V
150
40
300
50
ps
Output Duty Cycle
%
All parameters measured at fMAX unless noted otherwise. See Parameter Measurement Information.
NOTE 1: Measured from the differential input crossing point to the output at VDD/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDD/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDD/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83026AMI
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REV. B NOVEMBER 9, 2004
4
ICS83026I
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVCMOS/LVTTL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 0.15V
VDD
SCOPE
VDD
nCLK
Qx
LVCMOS
GND
VPP
VCMR
Cross Points
CLK
GND
-1.65V 0.15V
3.3VCORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
Qx
VDDO
2
VDDO
Qx
Qy
2
PART 2
Qy
VDDO
VDDO
2
2
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK
80%
tF
80%
CLK
20%
20%
VDDO
2
Clock
Outputs
tR
Q0, Q1
t
PD
P
ROPAGATION
D
ELAY
O
UTPUT
R
ISE/FALL
T
IME
VDDO
2
Q0, Q1
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
O
UTPUT
D
UTY
CYCLE/PULSE WIDTH/PERIOD
83026AMI
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REV. B NOVEMBER 9, 2004
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ICS83026I
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVCMOS/LVTTL FANOUT
BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
83026AMI
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REV. B NOVEMBER 9, 2004
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ICS83026I
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVCMOS/LVTTL FANOUT
BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 2A to 2E show inter- For example in Figure 2A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
83026AMI
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REV. B NOVEMBER 9, 2004
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ICS83026I
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVCMOS/LVTTL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 5. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83026I is: 416
83026AMI
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REV. B NOVEMBER 9, 2004
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ICS83026I
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVCMOS/LVTTL FANOUT
BUFFER
PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC
TABLE 6. PACKAGE DIMENSIONS
Millimeters
MINIMUM MAXIMUM
SYMBOL
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
83026AMI
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REV. B NOVEMBER 9, 2004
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ICS83026I
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVCMOS/LVTTL FANOUT
BUFFER
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS83026AMI
Marking
83026AMI
83026AMI
83026AIL
Package
Count
96 per tube -40°C to 85°C
2500 -40°C to 85°C
96 per tube -40°C to 85°C
2500 -40°C to 85°C
Temperature
8 Lead SOIC
ICS83026AMIT
ICS83026AMILF
8 Lead SOIC on Tape and Reel
8 Lead "Lead-Free" SOIC
8 Lead "Lead-Free" SOIC on
Tape and Reel
ICS83026AMILFT
83026AIL
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
83026AMI
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REV. B NOVEMBER 9, 2004
10
ICS83026I
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVCMOS/LVTTL FANOUT
BUFFER
REVISION HISTORY SHEET
Description of Change
Revised General Description.
Rev
Table
Page
Date
A
1
1
8/9/02
Added Lead-Free bullet to Features section.
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical
and added 5Ω min. & 12Ω max. to ROUT row.
Added Application Information section.
T2
T7
2
B
11/9/04
6-7
11
Added Lead-Free P/N to Ordering Information table.
83026AMI
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REV. B NOVEMBER 9, 2004
11
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