ICS8343AY-01 [ICSI]
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER; 低偏移， 1至16 LVCMOS / LVTTL扇出缓冲器
| 型号： | ICS8343AY-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER |
| 文件： | 总10页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8343-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8343-01 is a low skew, 1-to-16 LVCMOS/
• 16 LVCMOS/LVTTL outputs
• 1 LVCMOS/LVTTL clock input
ICS
LVTTL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS.The ICS8343-01 single ended
clock input accepts LVCMOS or LVTTL input levels.
HiPerClockS™
• CLK can accept the following input levels: LVCMOS, LVTTL
• Maximum output frequency: 200MHz
The ICS8343-01 operates at 3.3V, 2.5V and mixed 3.3V input and
2.5V supply modes over the commercial temperature range.
Guaranteed output and part-to-part skew characteristics make
the ICS8343-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
• Dual output enable inputs facilitates 1-to-16 or 1-to-8 input
to output modes
• All inputs are 5V tolerant
• Output skew: 250ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Full 3.3V and 2.5V or mixed 3.3V core/2.5V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
VDD2
VDD1
VDD
32 31 30 29 28 27 26 25
CLK
VDD1
VDD1
VDD1
Q3
VDD2
VDD2
VDD2
Q12
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q15
Q0
Q
1
4
Q1
ICS8343-01
Q13
Q
2
Q4
Q11
Q12
Q3
GND
GND
GND
GND
GND
GND
Q11
Q4
Q10
Q5
9
10 11 12 13 14 15 16
Q9
Q6
Q8
Q7
32-Lead LQFP
7mm x 7mm x 1.4mm body package
OE1
GND
OE2
Y Package
(TopView)
8343AY-01
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 16, 2004
1
ICS8343-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Description
Q0 thru Q7 output supply pins.
Number
1, 2, 3
4, 5
Name
VDD1
Type
Power
Output
Q3, Q4
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
Power supply ground.
6, 7, 8,
17, 18, 19
GND
Power
9, 10, 11
12
Q5, Q6, Q7
CLK
Output
Input
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
Pulldown LVCMOS/LVTTL clock input / 5V tolerant.
Core supply pin.
13
VDD
Power
Output
Output
Power
Output
14, 15, 16
20, 21
22, 23, 24
Q8, Q9, Q10
Q11, Q12
VDD2
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
Q8 thru Q15 output supply pins.
25, 26, 27 Q13, Q14, Q15
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
Output enable. When low forces outputs Q8 thru Q15 to HiZ state.
5V tolerant. LVCMOS/LVTTL interface levels.
Output enable. When low forces outputs Q0 thru Q7 to HiZ state.
5V tolerant. LVCMOS/LVTTL interface levels.
28
OE2
Input
Pullup
Pullup
29
OE1
Input
30, 31, 32
Q0, Q1, Q2
Output
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
pF
KΩ
KΩ
Ω
VDD, VDD1, VDD2 = 3.465V
VDD1, VDD2 = 2.63V
11
9
Power Dissipation Capacitance
(per output)
CPD
RPULLUP
Input Pullup Resistor
51
51
7
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
VDD, VDD1, VDD2 = 3.3V
5
12
TABLE 3. FUNCTION TABLE
Inputs
Outputs
OE1
OE2
Q0:Q7
Q8:Q15
HiZ
0
1
0
1
0
0
1
1
HiZ
Active
HiZ
HiZ
Active
Active
Active
NOTE: OE1 and OE2 are 5V tolerant.
8343AY-01
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 16, 2004
2
ICS8343-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDx + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDD1 = VDD2 = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = 0° TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
Core Supply Voltage
3.135
3.135
2.375
3.3
3.3
2.5
3.465
3.465
2.625
35
V
V
VDDx
Output Supply Voltage; NOTE 1
V
IDD
Power Supply Current
mA
mA
IDDx
Output Supply Current; NOTE 2
14
NOTE 1: VDDx denotes VDD1 and VDD2
.
NOTE 2: IDDx denotes the sum of IDD1 and IDD2
.
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 2.5V 5ꢀ, TA = 0° TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDx
IDD
Core Supply Voltage
2.375
2.375
2.5
2.5
2.625
2.625
34
V
Output Supply Voltage; NOTE 1
Power Supply Current
V
mA
mA
IDDx
Output Supply Current; NOTE 2
13
NOTE 1: VDDx denotes VDD1 and VDD2
.
NOTE 2: IDDx denotes the sum of IDD1 and IDD2
.
8343AY-01
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 16, 2004
3
ICS8343-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 3.3V 5ꢀ OR 2.5V 5ꢀ;
VDD = 3.3V 5ꢀ, VDD1 = VDD2 = 2.5V 5ꢀ, TA = 0° TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
OE1, OE2
CLK
2
2
V
V
DD + 0.3
DD + 0.3
0.8
V
V
VIH
VIL
IIH
Input High Voltage
OE1, OE2
CLK
-0.3
V
Input Low Voltage
Input High Current
-0.3
1.3
V
OE1, OE2
CLK
VDD = VIN = 3.465V or 2.625V
5
µA
µA
V
DD = VIN = 3.465V or 2.625V
150
VDD = 3.465V or 2.625V,
VIN = 0V
OE1, OE2
CLK
-150
-5
µA
µA
IIL
Input Low Current
VDD = 3.465V or 2.625V,
VIN = 0V
V
DD1 = VDD2 = 3.465V
VDD1 = VDD2 = 2.625V
VDD1 = VDD2 = 3.465V or 2.625V
2.6
1.8
V
V
VOH
Output High Voltage; NOTE 1
VOL
IOZL
IOZH
Output Low Voltage; NOTE 1
Output Tristate Current Low
Output Tristate Current High
0.5
5
V
µA
µA
5
NOTE 1: Outputs terminated with 50Ω to VDDx/2. See Parameter Measurement Information,
"Output Load Test Circuit Diagrams".
TABLE 5A. AC CHARACTERISTICS, VDD = VDD1 = VDD2 = 3.3V 5ꢀ, TA = 0° TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
200
MHz
Propagation Delay;
NOTE 1
tpLH
IJ 200MHz
2.0
4.0
250
700
ns
ps
ps
tsk(o)
tsk(pp)
Output Skew; NOTE 2, 4 Measured on rising edge @VDDx/2
Part-to-Part Skew;
Measured on rising edge @VDDx/2
NOTE 3, 4
tR / tF
odc
tPW
Output Rise/Fall Time
Output Duty Cycle
Output Pulse Width
20ꢀ to 80ꢀ
IJ 133MHz
ƒ> 133MHz
0.4
45
1.5
55
ns
ꢀ
tPERIOD/2 - 0.25 tPERIOD/2 tPERIOD/2 + 0.25
ns
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDx/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDx/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8343AY-01
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 16, 2004
4
ICS8343-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDD1 = VDD2 = 2.5V 5ꢀ, TA = 0° TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
200
4.5
250
700
1.0
60
MHz
ns
tpLH
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
IJ 200MHz
Measured on rising edge @VDDx/2
Measured on rising edge @VDDx/2
20ꢀ to 80ꢀ
2.0
tsk(o)
tsk(pp)
tR / tF
odc
ps
ps
0.4
40
ns
Output Duty Cycle
IJ 133MHz
ꢀ
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDx/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDx/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = VDD2 = 3.3V 5ꢀ, VDD1 = 2.5V 5ꢀ, TA = 0° TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
200
MHz
Measured on rising edge
@VDDx/2
tsk(o)
Output Skew; NOTE 1
250
ps
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Defined as skew across outputs at the same supply voltages within a bank, and with equal load conditions.
TABLE 5D. AC CHARACTERISTICS, VDD = VDD1 = VDD2 = 2.5V 5ꢀ, TA = 0° TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
133
4.0
250
1
MHz
ns
tpLH
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
IJ 200MHz
Measured on rising edge @VDDx/2
Measured on rising edge @VDDx/2
20ꢀ to 80ꢀ
2.0
tsk(o)
tsk(pp)
tR / tF
odc
ps
ns
0.4
40
1.0
60
ns
Output Duty Cycle
IJ 133MHz
ꢀ
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDx/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDx/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8343AY-01
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 16, 2004
5
ICS8343-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
2.05V 5ꢀ 1.25V 5ꢀ
1.65V 5ꢀ
SCOPE
SCOPE
VDD
VDD1
,
VDD
,
VDD2
V
DD1,VDD2
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V CORE/ 3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V 5ꢀ
VDDx
SCOPE
VDD
VDD1
VDD2
,
Qx
Qy
2
,
Qx
LVCMOS
VDDx
2
GND
tsk(o)
-1.25V 5ꢀ
2.5V CORE/ 2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
VDDx
2
Part 1
Qx
VDDx
2
Q0:Q15
Pulse Width
tPERIOD
Part 2
Qy
VDDx
2
tPW
tsk(pp)
odc =
tPERIOD
PART-TO-PART SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDDx
80ꢀ
80ꢀ
tR
2
CLK
20ꢀ
20ꢀ
Clock
Outputs
VDDx
tF
2
Q0:Q15
t
PD
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
www.icst.com/products/hiperclocks.html
8343AY-01
REV. B SEPTEMBER 16, 2004
6
ICS8343-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8343-01 is: 985
8343AY-01
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 16, 2004
7
ICS8343-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
8343AY-01
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 16, 2004
8
ICS8343-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS8343AY-01
ICS8343AY-01T
ICS8343AY-01LF
ICS8343AY-01
ICS8343AY-01
ICS8343AY01L
32 Lead LQFP
32 Lead LQFP on Tape and Reel
32 Lead "Lead-Free" LQFP
250 per tray
32 Lead "Lead-Free" LQFP on
Tape and Reel
ICS8343AY-01LFT
ICS8343AY01L
1000
0°C to 70°C
The aforementioned trademark, HiPerClockS™ and FEMTOCLOCKS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
8343AY-01
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 16, 2004
9
ICS8343-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
T2
2
Pin Characteristics Table - changed CIN 4pF max to 4pF typical.
Added to ROUT, 5Ω min. and 12Ω max.
A
9/18/03
T8
T5C
11
5
Ordering Information correct package column from 48 Lead to 32 Lead.
Added Mixed AC Characteristics Table.
Updated format.
B
B
8/13/04
9/16/04
T8
9
Added Lead-Free marking to Ordering Information Table.
8343AY-01
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 16, 2004
10
相关型号：
ICS8343AYI-01LFT
Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
IDT
©2020 ICPDF网 联系我们和版权申明