ICS8344BY [ICSI]
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER; 低偏移， 1至24差分至LVCMOS扇出缓冲器
| 型号： | ICS8344BY |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER |
| 文件： | 总15页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8344
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8344 is a low voltage, low skew fanout
• 24 LVCMOS outputs, 7Ω typical output impedance
,&6
buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8344 is designed to translate any
differential signal levels to LVCMOS levels. The
• Output frequency up to 167MHz
HiPerClockS™
• 275ps output skew, 600ps part to part skew
• Translates any differential input signal (PECL, HSTL, LVDS)
to LVCMOS without external bias networks
low impedance LVCMOS outputs are designed to drive 50Ω
series or parallel terminated transmission lines. The effective
fanout can be increased to 48 by utilizing the ability of the
outputs to drive two series terminated lines. Redundant clock
applications can make use of the dual clock input. The dual
clock inputs also facilitate board level testing. ICS8344 is
characterized at full 3.3V, full 2.5V and mixed 3.3V input and
2.5V output operating supply modes.
• Translates any single-ended input signal to LVCMOS with
resistor bias on nCLK input
• Translates and inverts any single-ended input signal to
LVCMOS with resistor bias on CLK input
• Multiple differential clock input pairs for redundant clock
applications
Guaranteed output and part-to-part skew characteristics
make the ICS8344 ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
• LVCMOS control inputs
• Multiple output enable pins for disabling unused outputs in
reduced fanout applications
• 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
• 48 lead low-profile QFP(LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
• 0°C to 70°C ambient operating temperature
• Industrial temperature versions available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
48 47 46 45 44 43 42 41 40 39 38 37
Q16
Q17
1
36
35
34
33
32
31
30
29
28
27
26
25
Q7
CLK0
nCLK0
2
0
Q6
VDDO
GND
Q18
3
VDDO
GND
Q5
CLK1
4
1
nCLK1
Q0 - Q7
OE1
5
Q19
6
Q4
ICS8344
Q20
7
Q3
Q21
8
Q2
O8 - Q15
VDDO
GND
Q22
9
VDDO
GND
Q1
10
11
12
OE2
O16 - Q23
Q23
Q0
13 14 15 16 17 18 19 20 21 22 23 24
OE3
48-Lead LQFP
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8344
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REV. B FEBRUARY 2, 2001
1
PRELIMINARY
ICS8344
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 5, 6
7, 8, 11, 12
Q16, Q17, Q18, Q19
Q20, Q21, Q22, Q23
Output
Q15 thru Q23 outputs. 7Ω typical output impedance.
3, 9, 28,
34, 39, 45
4, 10, 14,18,
27, 33, 40, 46
VDDO
GND
Power
Power
Input
Output power supply. Connect 3.3V or 2.5V.
Power supply ground. Connect to ground.
Clock select input. Selects between CLK0, nCLK0 and CLK1,
nCLK1 as the differential pair that controls the output.
13
CLK_SEL
Pulldown
15, 19
16
VDDI
nCLK1
CLK1
Power
Input
Input
Input
Input
Input power supply. Connect 3.3V or 2.5V.
Pullup
Inverting input of secondary differential clock input pair.
17
Pulldown Non-inverting input of secondary differential clock input pair.
Pullup Inverting input of primary differential clock input pair.
20
nCLK0
CLK0
21
Pulldown Non-inverting input of primary differential clock input pair.
Output enable. Controls enabling and disabling of outputs
Q16 thru Q23.
Output enable. Controls enabling and disabling of outputs
Q8 thru Q15.
Output enable. Controls enabling and disabling of outputs
Q0 thru Q7.
22
23
24
OE3
OE2
OE1
Input
Input
Pullup
Pullup
Input
Pullup
25, 26, 29, 30
31, 32, 35, 36
37, 38, 41, 42
Q0, Q1, Q2, Q3
Q4, Q5, Q6, Q7
Q8, Q9, Q10, Q11
Output
Output
Q0 thru Q7 outputs. 7Ω typical output impedance.
Q8 thru Q15 outputs. 7Ω typical output impedance.
43, 44, 47, 48 Q12, Q13, Q14, Q15
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CLK0, nCLK0,
CLK1, nCLK1
CLK_SEL,
pF
Input
Capacitance
CIN
pF
pF
pF
pF
OE1, OE2, OE3
VDDI, VDDO = 3.465V
Power Dissipation Capacitance
(per output)
VDDI = 3.465V, VDDO =
2.625V
CPD
VDDI, VDDO = 2.625V
RPULLUP
Input Pullup Resistor
51
51
7
KΩ
KΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
8344
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REV. B FEBRUARY 2, 2001
2
PRELIMINARY
ICS8344
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
Bank 1
Bank 2
Bank 3
Input
OE1
0
Output
Q0-Q7
Hi-Z
Input
OE2
0
Output
Q8-Q15
Hi-Z
Input
OE3
0
Output
Q16-Q23
Hi-Z
1
Active
1
Active
1
Active
TABLE 3B. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
CLK0, nCLK0
CLK1, nCLK1
0
1
Selected
De-selected
Selected
De-selected
TABLE 3C. CLOCK INPUTS FUNCTION TABLE
Inputs
Outputs
Q0 thru Q23
LOW
Input to Output Mode
Polarity
OE1, OE2, OE3
CLK
nCLK
1
1
1
1
1
1
0
1
Differential to Single Ended
Differential to Single Ended
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
HIGH
0
Biased; NOTE 1
LOW
1
Biased; NOTE 1
HIGH
Biased; NOTE 1
Biased; NOTE 1
0
1
HIGH
LOW
Inverting
NOTE 1: Single ended input use requires that one of the differential inputs be biased. The voltage at the biased input sets
the switch point for the single ended input. For LVCMOS input levels the recommended input bias network is a resistor to
VDDI, a resistor of equal value to ground and a 0.1µF capacitor from the input to ground. The resulting switch point is
VDDI/2.
8344
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REV. B FEBRUARY 2, 2001
3
PRELIMINARY
ICS8344
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
4.6V
Inputs
Outputs
Ambient Operating Temperature
Storage Temperature
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
0°C to 70°C
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of product at these condition or any conditions beyond those listed
in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDI = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDDI
Input Power Supply Voltage
3.135
2.375
3.3
2.5
3.465
2.625
V
V
VDDO
Output Power Supply Voltage
VDDI = VIH = 3.465V
VIL = 0V
IDDI
Quiescent Power Supply Current
120
mA
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDDI = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
5
µA
µA
µA
µA
IIH
IIL
Input High Current
150
-150
-5
Input Low Current
NOTE: For CLKx, nCLKx input levels, see VPP and VCMR in AC Characteristics table.
TABLE 4C. LVCMOS DC CHARACTERISTICS, VDDI = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK_SEL,
OE1, OE2, OE3
CLK_SEL,
VIH
VIL
Input High Voltage
VDDI = 3.465V
2
3.8
0.8
V
V
Input Low Voltage
Input High Current
VDDI = 3.135V
-0.3
OE1, OE2, OE3
OE1, OE2, OE3
CLK_SEL
VDDI = VIN = 3.465V
VDDI = VIN = 3.465V
VDDI = 3.465, VIN = 0V
VDDI = 3.465, VIN = 0
5
µA
µA
µA
µA
IIH
IIL
150
OE1, OE2, OE3
CLK_SEL
-150
-5
Input Low Current
VDDI = VDDO = 3.135V
IOH = -36mA
VDDI = VDDO = 3.135V
IOL = 36mA
VOH
VOL
Output High Voltage
Output Low Voltage
2.6
V
V
0.6
8344
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REV. B FEBRUARY 2, 2001
4
PRELIMINARY
ICS8344
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 5A. AC ELECTRICAL CHARACTERISTICS, VDDI = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
VPP
Maximum Input Frequency
Peak-to-Peak Input Voltage
167
1.3
2
MHz
V
f = 167MHz
f = 167MHz
0.3
0.9
2.6
2.4
VCMR Common Mode Input Voltage
V
tpLH
tpHL
Propagation Delay, Low-to-High
Propagation Delay, High-to-Low
0MHz ≤ f ≤ 167MHz
0MHz ≤ f ≤ 167MHz
4.3
4.3
ns
ns
Measured on the rising edge of
VDDO/2
tsk(b)
tsk(o)
Bank Skew; NOTE 2
Output Skew; NOTE 3
150
275
600
ps
ps
ps
Measured on the rising edge of
VDDO/2
Measured on the rising edge of
VDDO/2
tsk(pp) Part-to-Part Skew; NOTE 4
tR
tF
Output Rise Time; NOTE 5
Output Fall Time; NOTE 5
30% to 70%
30% to 70%
200
200
1000
1000
ps
ps
tCYCLE/2-
- 0.65
tCYCLE/2
+ 0.65
0MHz ≤ f ≤ 167MHz
tCYCLE/2
2.5
ns
tPW
Output Pulse Width
f = 167MHz
f = 66.7MHz
f = 66.7MHz
2.35
3.65
5
ns
ns
ns
tEN
Output Enable Time; NOTE 5
Output Disable TIme; NOTE 5
tDIS
4
NOTE 1: All parameters measured at 167MHz and VPPmin unless noted otherwise.
All outputs terminated with 50Ω to VDDO/2.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as the skew at different outputs on different devices operating at the same supply voltages
with equal load conditions.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
8344
www.icst.com
REV. B FEBRUARY 2, 2001
5
PRELIMINARY
ICS8344
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDDI = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDDI
Input Power Supply Voltage
3.135
2.375
3.3
2.5
3.465
2.625
V
V
VDDO
Output Power Supply Voltage
VDDI = VIH = 3.465V
VIL = 0V
IDDI
Quiescent Power Supply Current
120
mA
TABLE 4E. DIFFERENTIAL DC CHARACTERISTICS, VDDI = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
5
µA
µA
µA
µA
IIH
IIL
Input High Current
150
-150
-5
Input Low Current
NOTE: For CLKx, nCLKx input levels, see VPP and VCMR in AC Characteristics table.
TABLE 4F. LVCMOS DC CHARACTERISTICS, VDDI = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK_SEL,
OE1, OE2, OE3
CLK_SEL,
VIH
VIL
Input High Voltage
VDDI = 3.465V
2
3.8
.8
V
V
Input Low Voltage
Input High Current
VDDI = 3.465V
-0.3
OE1, OE2, OE3
OE1, OE2, OE3
CLK_SEL
VDDI = VIN = 3.465V
VDDI = VIN = 3.465V
VDDI = 3.465, VIN = 0V
VDDI = 3.465, VIN = 0
5
µA
µA
µA
µA
IIH
IIL
150
OE1, OE2, OE3
CLK_SEL
-150
-5
Input Low Current
VDDI = 3.135V,
VDDO = 2.375V
IOH = -36mA
VDDI = 3.135V,
VDDO = 2.365V
IOL = 27mA
VOH
VOL
Output High Voltage
1.8
V
V
Output Low Voltage
0.63
8344
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REV. B FEBRUARY 2, 2001
6
PRELIMINARY
ICS8344
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 5B. AC ELECTRICAL CHARACTERISTICS, VDDI = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
fMAX
VPP
Maximum Input Frequency
167
1.3
2
MHz
V
Peak-to-Peak Input Voltage
f = 167MHz
f = 167MHz
0.3
0.9
2.6
2.6
VCMR
tpLH
Common Mode Input Voltage
Propagation Delay, Low-to-High
Propagation Delay, High-to-Low
V
0MHz ≤ f ≤ 167MHz
0MHz ≤ f ≤ 167MHz
4.5
4.2
ns
ns
tpHL
Measured on the rising edge of
VDDO/2
tsk(b)
tsk(o)
tsk(pp)
Bank Skew; NOTE 2
150
275
600
ps
ps
ps
Measured on the rising edge of
VDDO/2
Output Skew; NOTE 3
Part-to-Part Skew; NOTE 4
Measured on the rising edge of
VDDO/2
tR
tF
Output Rise Time; NOTE 5
Output Fall Time; NOTE 5
30% to 70%
30% to 70%
300
300
1700
1400
ps
ps
tCYCLE/2
tCYCLE/2
- 0.65
tCYCLE/2
+ 0.65
0MHz ≤ f ≤ 167MHz
ns
tPW
Output Pulse Width
f = 167MHz
f = 66.7MHz
f = 66.7MHz
2.35
3.65
6
ns
ns
ns
tEN
Output Enable Time; NOTE 5
Output Disable TIme; NOTE 5
tDIS
6
NOTE 1: All parameters measured at 167MHz and VPPmin unless noted otherwise.
All outputs terminated with 50Ω to VDDO/2.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as the skew at different outputs on different devices operating at the same supply voltages
with equal load conditions.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
8344
www.icst.com
REV. B FEBRUARY 2, 2001
7
PRELIMINARY
ICS8344
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 4G. POWER SUPPLY DC CHARACTERISTICS, VDDI = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDDI
Input Power Supply Voltage
2.375
2.375
2.5
2.5
2.625
2.625
V
V
VDDO
Output Power Supply Voltage
VDDI = VIH = 3.465V
VIL = 0V
IDDI
Quiescent Power Supply Current
120
mA
TABLE 4H. DIFFERENTIAL DC CHARACTERISTICS, VDDI = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
5
µA
µA
µA
µA
IIH
IIL
Input High Current
150
-150
-5
Input Low Current
NOTE: For CLKx, nCLKx input levels, see VPP and VCMR in AC Characteristics table.
TABLE 4I. LVCMOS DC CHARACTERISTICS, VDDI = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK_SEL,
OE1, OE2, OE3
CLK_SEL,
VIH
VIL
Input High Voltage
VDDI = 2.625V
2
2.9
0.8
V
V
Input Low Voltage
Input High Current
VDDI = 2.375V
-0.3
OE1, OE2, OE3
OE1, OE2, OE3
CLK_SEL
VDDI = VIN = 2.625V
VDDI = VIN = 2.625V
VDDI = 2.625, VIN = 0V
VDDI = 2.625, VIN = 0
5
µA
µA
µA
µA
IIH
IIL
150
OE1, OE2, OE3
CLK_SEL
-150
-5
Input Low Current
VDDI = VDDO = 2.375V
IOH = -27mA
VDDI = VDDO = 2.375V
IOL = 27mA
VOH
VOL
Output High Voltage
Output Low Voltage
1.77
V
V
0.6
8344
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REV. B FEBRUARY 2, 2001
8
PRELIMINARY
ICS8344
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 5C. AC ELECTRICAL CHARACTERISTICS, VDDI = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
VPP
Maximum Input Frequency
167
1.3
2
MHz
V
Peak-to-Peak Input Voltage
f = 167MHz
f = 167MHz
0.3
0.9
2.7
2.7
VCMR
tpLH
Common Mode Input Voltage
Propagation Delay, Low-to-High
Propagation Delay, High-to-Low
V
0MHz ≤ f ≤ 167MHz
0MHz ≤ f ≤ 167MHz
4.3
4.3
ns
ns
tpHL
Measured on the rising edge of
VDDO/2
tsk(b)
tsk(o)
Bank Skew; NOTE 2
Output Skew; NOTE 3
150
275
600
ps
ps
ps
Measured on the rising edge of
VDDO/2
Measured on the rising edge of
VDDO/2
tsk(pp) Part-to-Part Skew; NOTE 4
tR
tF
Output Rise Time; NOTE 5
Output Fall Time; NOTE 5
30% to 70%
30% to 70%
300
300
1700
1400
ps
ps
tCYCLE/2
- 0.65
tCYCLE/2
+ 0.65
0MHz ≤ f ≤ 167MHz
tCYCLE/2
ns
tPW
Output Pulse Width
f = 167MHz
f = 66.7MHz
f = 66.7MHz
2.35
3.65
6
ns
ns
ns
tEN
Output Enable Time; NOTE 5
Output Disable TIme; NOTE 5
tDIS
6
NOTE 1: All parameters measured at 167MHz and VPPmin unless noted otherwise.
All outputs terminated with 50 Ω to VDDO/2.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as the skew at different outputs on different devices operating at the same supply voltages
with equal load conditions.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
8344
www.icst.com
REV. B FEBRUARY 2, 2001
9
PRELIMINARY
ICS8344
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
FIGURE 1A, 1B, 1C - INPUT CLOCK WAVEFORMS
VDDI
CLK
CROSS POINTS
VPP
VCMR
nCLK
GND
FIGURE 1A - LVDS, HSTL DIFFERENTIAL INPUT LEVELS
VDDI
CLK
CROSS POINTS
VCMR
VPP
nCLK
GND
FIGURE 1B - LVPECL DIFFERENTIAL INPUT LEVEL
VDDI
GND
CLK
or
nCLK
FIGURE 1C- LVCMOS AND LVTTL SINGLE ENDED INPUT LEVEL
8344
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REV. B FEBRUARY 2, 2001
10
PRELIMINARY
ICS8344
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
FIGURE 2A, 2B - TIMING WAVEFORMS
CLK
VPP
nCLK
tPHL
tPLH
Q
VDDO/2
FIGURE 2A - PROPAGATION DELAYS
fin = 167MHz, Vpp = 300mV, tr = tf = 200ps
OEx
3.3V
0V
OEx
Q
tPHZ
tPLZ
tPZH
tPZL
VOH
VOH - 300mV
VDDO/2
VDDO/2
VOL
VOL + 300mV
Q
FIGURE 2B - DISABLE AND ENABLE TIMES
fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps
8344
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REV. B FEBRUARY 2, 2001
11
PRELIMINARY
ICS8344
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
FIGURE 3A, 3B- SKEW DEFINITIONS & WAVEFORMS
Bank Skew - Skew between outputs within a bank. Outputs operating at the same temperature, supply voltages and with equal
load conditions.
CLK
VPP
nCLK
Q0, Q8, Q16
VDDO/2
VDDO/2
tsk(b)
tsk(b)
Q7, Q15, Q23
VDDO/2
VDDO/2
FIGURE 3A - BANK SKEW
fin = 167MHz, Vpp = 300mV, tr = tf = 200ps
Output Skew - Skew between outputs of any bank. Outputs operating at the same temperature, supply voltages and with equal
load conditions.
CLK
VPP
nCLK
Q0 - Q7
VDDO/2
VDDO/2
tsk(o)
tsk(o)
Q8 - Q15
Q16 - Q23
VDDO/2
VDDO/2
FIGURE 3B - OUTPUT SKEW
fin = 167MHz, Vpp = 300mV, tr = tf = 200ps
8344
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REV. B FEBRUARY 2, 2001
12
PRELIMINARY
ICS8344
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
FIGURE 4A - SKEW DEFINITIONS & WAVEFORMS
Part to Part Skew - Skew between outputs of any bank on different parts. Outputs operating at the same temperature, supply
voltages and with equal load conditions.
CLK
VPP
nCLK
PART 1
Q0 - Q7
Q8 - Q15
Q16 - Q23
VDDO/2
VDDO/2
tsk(p)
tsk(p)
PART 2
Q0 - Q7
Q8 - Q15
Q16 - Q23
VDDO/2
VDDO/2
FIGURE 4B - OUTPUT SKEW
fin = 167MHz, Vpp = 300mV, tr = tf = 200ps
8344
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REV. B FEBRUARY 2, 2001
13
PRELIMINARY
ICS8344
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
D
D2
θ
52
40
39
1
2
3
E
E1
E2
N
13
14
27
26
A
C
D1
A2
SEATING
-C-
PLANE
ccc
A1
b
c
TABLE 6. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BCC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
D
9.00 BASIC
7.00 BASIC
5.50
D1
D2
E
9.00 BASIC
7.00 BASIC
5.50
E1
E2
e
0.5 BASIC
0.60
L
0.45
0.75
0°
7°
ccc
0.08
Reference Document: JEDEC Publication 95, MS-026
8344
www.icst.com
REV. B FEBRUARY 2, 2001
14
ICS8344
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS8344BY
Marking
Package
48 Lead LQFP
Count
250 per tray
2000
Temperature
0°C to 70°C
0°C to 70°C
ICS8344BY
ICS8344BY
ICS8344BYT
48 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8344
www.icst.com
REV. B FEBRUARY 2, 2001
15
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