ICS83841 [ICSI]
20 BIT, DDR SDRAM 2:1 MUX; 20位， DDR SDRAM 2 ： 1 MUX
| 型号： | ICS83841 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 20 BIT, DDR SDRAM 2:1 MUX |
| 文件： | 总8页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83841
Integrated
Circuit
Systems, Inc.
20 BIT, DDR SDRAM 2:1 MUX
GENERAL DESCRIPTION
FEATURES
The ICS83841 is a 20 Bit, DDR SDRAM 2:1 MUX
• Forty low skew single-ended DIMM ports
• One SSTL-2 compatible select input
• Maximum Switching Speed: 3ns
• Output skew: 180ps (maximum)
• ron = 20Ω (typical)
ICS
HiPerClockS™
and is a member of the HiPerClockS™family of
High Performance Clock Solutions from ICS.The
device has 20 host lines and each host line can
be passed to 2 data ports. The host/data ports
are compatible with single-ended SSTL-2 and the device op-
erates from a 2.5V supply.
• Full 2.5V supply modes
Guaranteed low output skew makes the ICS83841 ideal for
demanding applications which require well defined performance
and repeatability.
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
LOGIC DIAGRAM
SIMPLIFIED SCHEMATIC
ron
DH0
DA0
DB0
Sw
Sw
DHx
DAx or DBx
RPD
ron
DH19
DA19
DB19
Sw
Sw
S
S
SW
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
A
B
C
D
E
F
DB17
DA18
DB18
DA19
DB19
DA0
DB0
DA1
DB1
DA2
DA17
DH17
DH18
GND
DH19
DH0
GND
DH1
DH2
DB2
DB16
DH16
DB15
DA16
DA15
DH15
GND
DB14
DH14
GND
DA14
DB13
DA13
DH13
DB12
DH12
DH11
GND
DH10
DH9
DA12
DB11
DA11
DB10
DA10
DB9
DA9
DB8
DA8
DB7
ICS83841
72-Ball TFBGA
6mm x 6mm x 1.2mm
package body
S
VDD
VDD
VDD
GND
DH8
G
H
J
H Package
Top View
GND
DH4
DB4
GND
DH5
DA5
DH3
DA3
DB3
DA4
DA6
DB5
DH6
DB6
DH7
DA7
K
83841BH
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REV.A JANUARY 20, 2006
1
ICS83841
Integrated
Circuit
Systems, Inc.
20 BIT, DDR SDRAM 2:1 MUX
TABLE 1. PIN DESCRIPTIONS
Number
E8, F3, F8
Name
VDD
Type Description
Power Positive supply pins.
Power Power supply ground.
C5, C6, D2, D9, G2, G9, H5, H6
GND
Control Input. Selects Host
Input
E3
S
Port function per Table 3.
B2, B3, B5, B6, B8, B9,
C2 C9, E2, E9, F2, F9, H2,
H9, J2, J3, J5, J6, J8, J9
DH17, DH16, DH15, DH14, DH13, DH12,
DH18, DH11, DH19, DH10, DH0, DH9, DH1,
DH8, DH2, DH3, DH4, DH5, DH6, DH7
DA17, DA15, DA14, DA13, DA12, DA18,
DA16, DA11, DA19, DA10, DA0, DA9, DA1,
DA6, DA8, DA2, DA3, DA4, DA5, DA7
DB17, DB16, DB15, DB14, DB12, DB13,
DB11, DB18, DB10, DB19, DB9, DB0, DB8,
DB1, DB3, DB2, DB4, DB5, DB6, DB7
Port Host ports.
Port DIMM ports.
Port DIMM ports.
A2, A5, A7, A8, A10, B1,
B4, C10, D1, E10, F1, G10, H1,
J7, J10, K1, K3, K4, K6, K9
A1, A3, A4, A6, A9, B7,
B10, C1, D10, E1, F10, G1, H10,
J1, J4, K2, K5, K7, K8, K10
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
VI = 0V or VDD
VIN = 1.5V
Minimum Typical Maximum Units
CIN
Control Pin Capacitance
Channel on Capacitance
5
pF
pF
CON
10
TABLE 3. FUNCTION TABLE
Control Input
S
Function
Host Port = B DIMM Ports
A DIMM Port = 140Ω to GND
Host Port = A DIMM Ports
B DIMM Port = 140Ω to GND
L
H
83841BH
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REV.A JANUARY 20, 2006
2
ICS83841
Integrated
Circuit
Systems, Inc.
20 BIT, DDR SDRAM 2:1 MUX
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
-0.5V to +3.3V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.3V to VDD + 0.3 V
I
Ports
DC Input Clamp Current, IIK
-50mA
Package Thermal Impedance, θJA 50.04°C/W (0 mps)
StorageTemperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 0.2V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
IDD
Positive Supply Voltage
Power Supply Current
2.3
2.5
20
2.7
V
µA
TABLE 4B. DC CHARACTERISTICS, VDD = 2.5V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
VIK
Input High Voltage
S
S
1.6
V
V
Input Low Voltage
0.9
-1.2
100
100
100
30
Input Clamp Voltage
VDD = 2.3V; II = -18mA
V
S
µA
µA
µA
Ω
VDD = 2.5V; VI = VDD or GND;
S = VDD
Input Leakage
Current
IL
Host Port
DIMM Port
S = GND for IIL(test)
VDD = 2.5V; VA = 0.8V; VB = 1.0V
VDD = 2.5V; VA = 1.7V; VB = 1.5V
16
16
20
20
rON
On Resistance; NOTE 1
30
Ω
NOTE 1: Measured by the current between the Host and the DIMM terminals at the indicated voltages on each side
of the switch.
TABLE 5. AC CHARACTERISTICS, VDD = 2.5V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Propagation Delay;
NOTE 1, 3
Output
Enable Time
Output
Disable Time
Output Skew;
NOTE 2, 3
From DHx or DAx/DBx
to DAx/DBx or DHx
From S to
tPD
125
240
ps
ns
ns
ps
tEN
1.2
1.2
DHx or DAx/DBx
From S to
DHx or DAx/DBx
tDIS
tOSK
Any Port to any Port
180
NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
NOTE 3: Not production tested, guaranteed by characterization.
83841BH
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REV.A JANUARY 20, 2006
3
ICS83841
Integrated
Circuit
Systems, Inc.
20 BIT, DDR SDRAM 2:1 MUX
PARAMETER MEASUREMENT INFORMATION
VDD = 1.25V 0.1V
VDD
2
SCOPE
VDD
DAx,
DBx
LVCMOS
GND
VDD
DAy,
DBy
2
tsk(o)
-1.25V 0.1V
This circuit is used for test purposes only,
not intended for application use.
2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
S
(Low-level
enabling)
2.5V
0V
2.5V
1.25V
1.25V
1.25V
Input
1.25V
0V
Rising Edge
Skew
FallingEdge
Skew
VOH
tPZH →
tPHZ
→
1.25V
VOL
1.25V
←
VOH
Output
VOH - 0.15V
Output DAx/DBx
(See Note)
1.25V
VOL
NOTE: The output is high except when disabled by the S control.
RISING & FALLING EDGE SKEW
3-STATE OUTPUT ENABLE/DISABLE TIMES
VDD
2
VDD
DAx
2
DHx
VDD
2
VDD
DBx
2
DAx/DBx
tsk(b)
t
PD
BANK SKEW
PROPAGATION DELAY
83841BH
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REV.A JANUARY 20, 2006
4
ICS83841
Integrated
Circuit
Systems, Inc.
20 BIT, DDR SDRAM 2:1 MUX
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR A 72-BALL TFBGA
θJA byVelocity (Millimeter Feet per Second)
0
1
2
Two-Layer PCB, JEDEC Standard Test Boards
50.04°C/W
43.18°C/W
41.17°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83841 is: 261
83841BH
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REV.A JANUARY 20, 2006
5
ICS83841
Integrated
Circuit
Systems, Inc.
20 BIT, DDR SDRAM 2:1 MUX
PACKAGE OUTLINE - H SUFFIX FOR A 72-BALL TFBGA
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
FBGA
MINIMUM
NOMINAL
MAXIMUM
SYMBOL
72 Balls, 6x6mm, 10x10 Pattern
A
A1
b
1.0
1.1
1.2
0.165
0.25
0.2
0.235
0.35
0.3
D
6.00 BSC
4.50 BSC
6.00 BSC
4.50 BSC
0.50 BSC
D1
E
E1
e
REFERENCE DOCUMENT:JEDEC PUBLICATION 95, MO-195
83841BH
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REV.A JANUARY 20, 2006
6
ICS83841
Integrated
Circuit
Systems, Inc.
20 BIT, DDR SDRAM 2:1 MUX
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS83841BH
ICS83841BHT
ICS83841BHLF
ICS83841BHLFT
ICS83841BH
ICS83841BH
72-Ball TFBGA
TBD
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
72-Ball TFBGA
2500 Tape & Reel
TBD
ICS83841BHLF
ICS83841BHLF
72-Ball, Lead Free, TFBGA
72-Ball, Lead Free, TFBGA
2500 Tape & Reel
NOTE: Parts that are ordered with an"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
83841BH
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REV.A JANUARY 20, 2006
7
ICS83841
Integrated
Circuit
Systems, Inc.
20 BIT, DDR SDRAM 2:1 MUX
REVISION HISTORY SHEET
Rev
Table
T8
Page
Description of Change
Ordering Information table - corrected Lead-Free marking and added
Lead-Free note.
Date
A
8
1/20/06
83841BH
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REV.A JANUARY 20, 2006
8
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