ICS83904AG-02T [ICSI]
LOW SKEW, 1-TO-4 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER; 低偏移， 1到4 CRYSTAL -TO - LVCMOS / LVTTL扇出缓冲器
| 型号： | ICS83904AG-02T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-4 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER |
| 文件： | 总15页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS83904-02
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83904-02 is a low skew, high perfor- • Four LVCMOS/LVTTL outputs,
ICS
mance 1-to-4 Crystal Oscillator/Crystal-to-
19Ω typical output impedance
HiPerClockS™
LVCMOS Fanout Buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS83904-02 has
• Two Crystal oscillator input pairs
One LVCMOS/LVTTL clock input
selectable single ended clock or two crystal-oscillator inputs.
There is an output enable to disable the outputs by placing them
into a high-impedance state.
• Crystal input frequencry range: 10MHz - 40MHz
• Output frequency: 200MHz (typical)
• Output Skew:TBD
Guaranteed output and part-to-part skew characteristics
make the ICS83904-02 ideal for those applications demanding
well defined performance and repeatability.
• Part to Part Skew: TBD
• RMS phase jitter @ 25MHz output, using a 25MHz crystal
(100Hz - 1MHz): 0.16ps (typical) @ VDD = VDDO = 3.3V
• RMS phase noise at 25MHz:
Offset
Noise Power
100Hz ..............-118.4 dBc/Hz
1kHz ..............-141.5 dBc/Hz
10kHz ..............-157.2 dBc/Hz
100kHz ..............-157.2 dBc/Hz
• SupplyVoltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
BLOCK DIAGRAM
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
Pullup
OE
Pulldown
CLK_SEL0
Pulldown
CLK_SEL1
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
CLK_SEL0
XTAL_OUT0
XTAL_IN0
VDD
XTAL_IN1
XTAL_OUT1
CLK_SEL1
CLK
16
15
14
13
12
11
10
9
VDDO
Q0
Q1
GND
Q2
Q3
XTAL_IN0
OSC
0 0
XTAL_OUT0
Q0
VDDO
OE
ICS83904-02
16-LeadTSSOP
4.4mm x 5.0mm x 0.92mm
package body
XTAL_IN1
OSC
4 LVCMOS Outputs
0 1
XTAL_OUT1
G Package
Top View
Q3
1 0
Pulldown
CLK
1 1
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83904AG-02
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REV. A JULY 8, 2005
1
PRELIMINARY
ICS83904-02
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
CLK_SEL0,
CLK_SEL1
XTAL_OUT0,
XTAL_IN0
Clock select inputs. See Table 3, Input Reference Function Table.
LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN0 is the input.
XTAL_OUT0 is the output.
1, 7
Input Pulldown
2, 3
4
Input
Power
Input
VDD
Core supply pin.
XTAL_IN1,
XTAL_OUT1
Crystal oscillator interface. XTAL_IN1 is the input.
XTAL_OUT1 is the output.
5, 6
8
CLK
Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. When LOW, outputs are in HIGH impedance state.
9
OE
Input
Pullup
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
10, 16
VDDO
Power
Output supply pins.
11, 12, 14, 15 Q3, Q2, Q1, Q0 Output
13 GND Power
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
51
51
8
pF
kΩ
kΩ
pF
pF
pF
Ω
RPULLUP
RPULLDOWN Input Pulldown Resistor
VDDO = 3.465V
VDDO = 2.625V
Power Dissipation Capacitance
(per output)
CPD
7
V
DDO = 2.0V
VDDO = 3.3V 5%
DDO = 2.5V 5%
VDDO = 1.8V 0.2V
7
19
TBD
TBD
ROUT
Output Impedance
V
Ω
Ω
TABLE 3. INPUT REFERENCE FUNCTION TABLE
Control Inputs
Reference
CLK_SEL1
CLK_SEL0
0
0
1
1
0
1
0
1
XTAL0 (default)
XTAL1
CLK
CLK
83904AG-02
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REV. A JULY 8, 2005
2
PRELIMINARY
ICS83904-02
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
SupplyVoltage, V
4.6V
DD
Inputs, V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.3
3.3
28
3.465
3.465
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
mA
mA
IDDO
50
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
2.375
3.3
2.5
28
3.465
2.625
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
mA
mA
IDDO
33
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
1.6
3.3
1.8
29
3.465
2.0
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
mA
mA
IDDO
25
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
2.375
2.375
2.5
2.5
15
2.625
2.625
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
mA
mA
IDDO
41
TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 5%, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
2.375
1.6
2.5
1.8
15
2.625
2.0
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
mA
mA
IDDO
32
83904AG-02
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REV. A JULY 8, 2005
3
PRELIMINARY
ICS83904-02
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
V
V
V
V
DD = 3.3V 5%
DD = 2.5V 5%
DD = 3.3V 5%
DD = 2.5V 5%
2.0
1.7
VDD + 0.3
VDD + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
-0.3
-0.3
Input Low Voltage
Input High Current
0.7
CLK,
CLK_SEL0:1
V
DD = 3.3V or 2.5V 5%
VDD = 3.3V or 2.5V 5%
DD = 3.3V or 2.5V 5%
150
5
µA
µA
µA
IIH
OE
CLK,
CLK_SEL0:1
V
-5
IIL
Input Low Current
Output HighVoltage
OE
VDD = 3.3V or 2.5V 5%
VDDO = 3.3V 5%; NOTE 1
-150
2.6
µA
V
VOH
V
DDO = 2.5V 5%; NOTE 1
DDO = 1.8V 0.2V; NOTE 1
VDDO = 3.3V 5%; NOTE 1
DDO = 2.5V 5%; NOTE 1
DDO = 1.8V 0.2V; NOTE 1
1.8
V
V
1.5
V
0.5
0.5
0.4
V
VOL
Output Low Voltage
V
V
V
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation / cut
Frequency
Fundamental
10
40
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
83904AG-02
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REV. A JULY 8, 2005
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PRELIMINARY
ICS83904-02
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
w/External XTAL
w/External CLK
10
40
MHz
MHz
fMAX
tpLH
Output Frequency
200
1.8
Propagation Delay, Low-to-High;
ns
NOTE 1
tsk(o)
Output Skew; NOTE 2
TBD
TBD
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
tjit(Ø)
0.16
ps
tR / tF
odc
tEN
Output Rise/Fall Time
20% to 80%
420
50
ps
%
Output Duty Cycle
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
10
8
ns
ns
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
TABLE 6B. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
w/External XTAL
w/External CLK
10
40
MHz
MHz
fMAX
tpLH
Output Frequency
200
2
Propagation Delay, Low-to-High;
ns
NOTE 1
tsk(o)
Output Skew; NOTE 2
TBD
TBD
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
tjit(Ø)
0.16
ps
tR / tF
odc
tEN
Output Rise/Fall Time
20% to 80%
440
50
ps
%
Output Duty Cycle
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
10
8
ns
ns
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
83904AG-02
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REV. A JULY 8, 2005
5
PRELIMINARY
ICS83904-02
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6C. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
w/External XTAL
w/External CLK
10
40
MHz
MHz
fMAX
tpLH
Output Frequency
200
2.3
Propagation Delay, Low-to-High;
ns
NOTE 1
tsk(o)
Output Skew; NOTE 2
TBD
TBD
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
tjit(Ø)
0.16
ps
tR / tF
odc
tEN
Output Rise/Fall Time
20% to 80%
490
50
ps
%
Output Duty Cycle
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
10
8
ns
ns
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
TABLE 6D. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
w/External XTAL
w/External CLK
10
40
MHz
MHz
fMAX
tpLH
Output Frequency
200
2.1
Propagation Delay, Low-to-High;
ns
NOTE 1
tsk(o)
Output Skew; NOTE 2
TBD
TBD
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
tjit(Ø)
0.20
ps
tR / tF
odc
tEN
Output Rise/Fall Time
20% to 80%
448
50
ps
%
Output Duty Cycle
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
10
8
ns
ns
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
83904AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 8, 2005
6
PRELIMINARY
ICS83904-02
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6E. AC CHARACTERISTICS, VDD = 2.5V 5%, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
w/External XTAL
w/External CLK
10
40
MHz
MHz
fMAX
tpLH
Output Frequency
200
2.4
Propagation Delay, Low-to-High;
ns
NOTE 1
tsk(o)
Output Skew; NOTE 2
TBD
TBD
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
tjit(Ø)
0.19
ps
tR / tF
odc
tEN
Output Rise/Fall Time
20% to 80%
490
50
ps
%
Output Duty Cycle
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
10
8
ns
ns
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
83904AG-02
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REV. A JULY 8, 2005
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PRELIMINARY
ICS83904-02
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TYPICAL PHASE NOISE AT 25MHZ
0
-10
-20
25MHz
RMS Phase Jitter (Random)
100Hz to 1MHz = 0.16ps (typical)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
Raw Phase Noise Data
-170
-180
-190
100
1k
10k
100k
1M
OFFSET FREQUENCY (HZ)
83904AG-02
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REV. A JULY 8, 2005
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PRELIMINARY
ICS83904-02
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 5%
1.25V 5%
SCOPE
SCOPE
VDD
VDDO
,
VDD
VDDO
,
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V 5%
-1.25V 5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.4V 0.065V 0.9V 0.1V
2.05V 5% 1.25V 5%
SCOPE
SCOPE
VDD
VDD
VDDO
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-0.9V 0.1V
-1.25V 5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.6V 0.025V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
0.9V 0.1V
Part 1
Qx
VDDO
2
SCOPE
VDD
VDDO
Qx
LVCMOS
Part 2
Qy
VDDO
GND
2
tsk(pp)
-0.9V 0.1V
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
PART-TO-PART SKEW
83904AG-02
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PRELIMINARY
ICS83904-02
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
VDD
2
80%
tF
80%
tR
CLK
20%
20%
VDDO
2
Clock
Outputs
Q0:Q3
tpLH
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
VDDO
2
Q0:Q3
tPW
tPERIOD
tPW
x 100%
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
83904AG-02
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REV. A JULY 8, 2005
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PRELIMINARY
ICS83904-02
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
suitable for most applications. Additional accuracy can be
achieved by adding two small capacitors C1 and C2 as shown in
Figure 1.Typical results using parallel 18pF crystals are shown
inTable 5.
A crystal can be characterized for either series or parallel mode
operation.The ICS83904-02 has a built-in crystal oscillator circuit.
This interface can accept either a series or parallel crystal without
additional components and generate frequencies with accuracy
XTAL_OUT
XTAL_IN
C1
15p
X1
18pF Parallel Crystal
C2
15p
Figure 1. Crystal Input Interface
83904AG-02
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REV. A JULY 8, 2005
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PRELIMINARY
ICS83904-02
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVCMOS OUTPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.Though
not required, but for additional protection, a 1kΩ resister can be
tied from XTAL_IN to ground.
All unused LVCMOS output can be left floating.We recommend
that there is no trace attached.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating.We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating.Though not required, but for additional protection, a
1kΩ resister can be tied from the CLK input to ground.
LVHSTL OUTPUT
All unused LVHSTL outputs can be left floating.We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
TEST CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating.Though not required, but for additional protection, a
1kΩ resister can be tied from the TEST_CLK to ground.
LVDS OUTPUT
All unused LVDS outputs should be terminated with 100Ω resister
between the differential pair.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resister can be tied from CLK
to ground.
LVDS – Like OUTPUT
All unused LVDS outputs can be left floating.We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resister can be tied
from PCLK to ground.
HCSL OUTPUT
All unused HCSL outputs can be left floating.We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
SELECT PINS:
SSTL OUTPUT
All select pins have internal pull-ups and pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resister can be used.
All unused SSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
83904AG-02
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REV. A JULY 8, 2005
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PRELIMINARY
ICS83904-02
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83904-02 is: 205
83904AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 8, 2005
13
PRELIMINARY
ICS83904-02
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
83904AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 8, 2005
14
PRELIMINARY
ICS83904-02
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS83904AG-02
Marking
Package
Shipping Packaging
tube
Temperature
0°C to 70°C
0°C to 70°C
83904A02
83904A02
16 Lead TSSOP
16 Lead TSSOP
ICS83904AG-02T
2500 tape & reel
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
83904AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 8, 2005
15
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