ICS83947AYI [ICSI]
LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER; 低偏移， 1到9 LVCMOS扇出缓冲器
| 型号： | ICS83947AYI |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER |
| 文件： | 总9页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83947I
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-9
LVCMOS FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83947I is a low skew, 1-to-9 LVCMOS
• 9 LVCMOS/LVTTL outputs
ICS
Fanout Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The low impedance LVCMOS/LVTTL out-
puts are designed to drive 50Ω series or parallel
• Selectable CLK0 and CLK1 can accept the following
input levels:LVCMOS and LVTTL
HiPerClockS™
• Maximum output frequency: 110MHz
• Output skew: 500ps (maximum)
• Part-to-part skew: 2ns (maximum)
• 3.3V operating supply
terminated transmission lines.The effective fanout can be in-
creased from 9 to 18 by utilizing the ability of the outputs to
drive two series terminated lines.
Guaranteed output and part-to-part skew characteristics
make the ICS83947I ideal for high performance, single ended
applications that also require a limited output voltage.
• -40°C to 85°C ambient operating temperature
• Lead-Free package available
• Pin compatible with the MPC947
BLOCK DIAGRAM
PIN ASSIGNMENT
D
CLK_EN
Q
LE
32 31 30 29 28 27 26 25
0
1
CLK0
CLK1
GND
Q3
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
CLK_SEL
CLK0
Q0
VDDO
Q4
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CLK1
CLK_SEL
ICS83947I
GND
Q5
CLK_EN
OE
VDDO
GND
VDD
GND
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
TopView
OE
83947AYI
http://www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
1
ICS83947I
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-9
LVCMOS FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Power
Input Pullup
Description
1, 8, 9, 12, 16, 17,
20, 24, 25, 29, 32
GND
Power supply ground.
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
2
CLK_SEL
3, 4
CLK0, CLK1
CLK_EN
OE
Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels.
Input Pullup Clock enable. LVCMOS / LVTTL interface levels.
Input Pullup Output enable. LVCMOS / LVTTL interface levels.
5
6
7
VDD
Power
Power
Coree supply pin.
Output supply pins.
10, 14, 18, 22, 27, 31
VDDO
11, 13, 15, 19, 21,
23, 26, 28, 30
Q8, Q7, Q6, Q5,
Q4, Q3, Q2, Q1, Q0
Q0 thru Q8 clock outputs.
LVCMOS / LVTTL interface levels.
Output
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
25
pF
RPULLUP
Input Pullup Resistor
51
51
7
KΩ
KΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
5
12
TABLE 3. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE
Control Inputs
Output
Q0:Q8
OE
CLK_EN
0
1
1
X
0
1
Hi-Z
LOW
Follows CLK input
83947AYI
http://www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
2
ICS83947I
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-9
LVCMOS FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature,T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Coret Supply Voltage
3.0
3.0
3.3
3.3
33
3.6
3.6
50
V
V
Output Supply Voltage
Input Supply Current
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
Input High Voltage
2
3.6
0.8
V
V
Input Low Voltage
CLK0, CLK1, CLK_SEL,
OE, CLK_EN
IIN
Input Current
-100
2.5
µA
VOH
VOL
Output High Voltage
Output Low Voltage
IOH = -20mA
IOL = 20mA
V
V
0.4
83947AYI
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REV. B OCTOBER 11, 2004
3
ICS83947I
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-9
LVCMOS FANOUT
BUFFER
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum
110
Typical
Maximum
Units
MHz
ns
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 5
CLK to Q
1.8
4.5
Measured on
rising edge @VDDO/2
tsk(o)
500
ps
ns
Measured on
rising edge @VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
2
tPW
tS
Output Pulse Width
tPeriod/2 - 800
tPeriod/2 + 800
ps
ns
ns
ns
ns
ns
ns
Clock Enable Setup Time; NOTE 6
Clock Enable Hold Time; NOTE 6
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
Output Rise Time
CLK_EN to CLK
CLK_EN to CLK
0
1
tH
tZL, tZH
tLZ, tHZ
tR
11
11
1
0.8V to 2.0V
0.8V to 2.0V
0.2
0.2
tF
Output Fall Time
1
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
83947AYI
http://www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
4
ICS83947I
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-9
LVCMOS FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 0.15V
VDDO
2
SCOPE
VDD
Qx
Qy
Qx
LVCMOS
VDDO
2
GND
tsk(o)
-1.65V 0.15V
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
PART 1
Qx
VDDO
2
VDD
2
CLK0,
CLK1
VDDO
PART 2
Qy
VDDO
2
Q0:Q8
t
2
tsk(pp)
PD
PROPAGATION DELAY
PART-TO-PART SKEW
VDDO
2
Q0:Q8
2V
2V
Pulse Width
tPERIOD
0.8V
0.8V
Clock
Outputs
tR
tF
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
83947AYI
http://www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
5
ICS83947I
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-9
LVCMOS FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83947I is: 1040
83947AYI
http://www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
6
ICS83947I
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-9
LVCMOS FANOUT
BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
83947AYI
http://www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
7
ICS83947I
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-9
LVCMOS FANOUT
BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS83947AYI
Marking
Package
32 Lead LQFP
Count
250 per tray -40°C to 85°C
1000 -40°C to 85°C
250 per tray -40°C to 85°C
Temperature
ICS83947AYI
ICS83947AYI
ICS83947AYIT
32 Lead LQFP on Tape and Reel
32 Lead "Lead-Free/Annealed"
LQFP
32 Lead "Lead-Free/Annealed"
LQFP on Tape and Reel
ICS83947AYILN
ICS83947AYILNT
ICS3947AYIN
ICS3947AYIN
1000
-40°C to 85°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
83947AYI
http://www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
8
ICS83947I
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-9
LVCMOS FANOUT
BUFFER
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
AC Characterisitics Table, tS and tH rows- revised Test Conditions to read
CLK_EN to CLK.
A
T5
4
6/21/02
1
2
Added Lead Free bullet in Features section.
T2
T8
Pin Characteristics Table - changed CIN from 4pF max. to 4pF min.
ROUT added 5Ω min and 12Ω max.
Ordering Information Table - add Lead-Free part.
B
10/11/04
8
Updated format throughout data sheet.
83947AYI
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REV. B OCTOBER 11, 2004
9
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