ICS840001AK-34 [ICSI]
FEMTOCLOCKS? CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER; FEMTOCLOCKS⑩ CRYSTAL -TO LVCMOS / LVTTL频率合成器
| 型号： | ICS840001AK-34 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER |
| 文件： | 总9页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS840001-34
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS840001-34 is a two output LVCMOS/ • (2) LVCMOS/LVTTL outputs, 20Ω typical output impedence
ICS
LVTTL Synthesizer and a member of the
HiPerClocksTM family of high performance
devices from ICS. One output is the LVCMOS/
LVTTL main synthesized clock output (Q) and
(1) Main clock output (Q)
(1)Three-state reference clock output (REF_CLK)
HiPerClockS™
• Crystal oscillator interface can accept crystals from
15.3125MHz to 42.67MHz, 18pF parallel resonant crystal
one output is a three-state LVCMOS/LVTTL reference
clock (REF_CLK) output at the frequency of the crystal
oscillator. The device can accept crystal from 15.3125MHz
to 42.67MHz and can synthesize outputs from 81.67MHz
to 213.33MHz.The ICS840001-34 has excellent <1ps
phase jitter performance over the 637kHz – 10MHz
integration range. The ICS840001-34 is packaged in a
3mm x 3mm 16-pin VFQFN, making it ideal for use on
space constrained boards.
• Output frequency range: 81.67MHz to 213.33MHz
• VCO range: 490MHz to 640MHz
• RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.38ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
COMMON APPLICATION CONFIGURATION TABLE
Inputs
Output Frequency
Application
Serial Attached (SCSI),
(MHz)
Crystal
M Divider
VCO (MHz)
N Divider
40
15
600
6
100
PCI Express™, Processor Clock
26.5625
40
24
15
24
25
25
25
32
637.5
600
6
4
3
5
4
3
4
106.25
150
Fibre Channel
Serial ATA (SATA), Processor Clock
Fibre Channel 2
26.5625
25
637.5
625
212.5
125
Ethernet
25
625
156.25
187.5
155.52
10 Gigabit Ethernet
12 Gigabit Ethernet
SONET
22.5
562.5
622.08
19.44
BLOCK DIAGRAM
PIN ASSIGNMENT
(Pullup)
OE
REF_CLK
16 15 14 13
OE
XTAL_IN
XTAL_OUT
M0
1
2
3
4
12
Q
11 VDDO
00 = ÷3
VCO
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
01 = ÷4
GND
VDD
10
9
Q
490MHz - 640MHz
10 = ÷5
11 = ÷6 (default)
5
6
7
8
11 = ÷15 (default)
10 = ÷24
01 = ÷25
00 = ÷32
ICS840001-34
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
(Pullup)
M1
Top View
(Pullup)
M0
(Pullup)
N1
(Pullup)
N0
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840001AK-34
www.icst.com/products/hiperclocks.html
REV. A MAY 6, 2005
1
PRELIMINARY
ICS840001-34
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
Output enable pin. When HIGH, REF_CLK output is enabled.
When LOW, forces REF_CLK to HiZ state.
LVCMOS/LVTTL interface levels.
1
OE
Input
Pullup
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
2,3
Input
Input
4, 5
M0, M1
nc
Pullup
Pullup
M divider inputs. LVCMOS/LVTTL interface levels. See Table 3B.
No connect.
6, 14, 15
Unused
Input
Determines output divider value as defined in Table 3C.
LVCMOS/LVTTL interface levels.
7, 8
N0, N1
9
VDD
GND
VDDO
Power
Power
Power
Core supply pin.
10
11
Power supply ground.
Output supply pin.
Single-ended clock output. LVCMOS/LVTTL interface levels.
20Ω typical output impedance.
12
Q
Output
Single-ended three-state reference clock output.
LVCMOS/LVTTL interface levels. 20Ω typical output impedance.
Analog supply pin.
13
16
REF_CLK
VDDA
Output
Power
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
8
pF
pF
kΩ
Ω
CPD
Power Dissipation Capacitance
Input Pullup Resistor
VDD, VDDA, VDDO = 3.465V
RPULLUP
ROUT
51
20
Output Impedance
TABLE 3A. CONTROL FUNCTION TABLE
Control Inputs
Output
REF_CLK
Hi-Z
OE
0
1
Active
TABLE 3B. M DIVIDER FUNCTION TABLE
Control Inputs
TABLE 3C. N DIVIDER FUNCTION TABLE
Control Inputs
Feedback Divider Ratio
Output Divider Ratio
M1
0
M0
0
N1
0
N0
0
÷32
÷25
÷3
÷4
0
1
0
1
1
0
÷24
1
0
÷5
1
1
÷15 (default)
1
1
÷6 (default)
840001-34AK
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REV. A MAY 6, 2005
2
PRELIMINARY
ICS840001-34
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
I
Outputs, VO
PackageThermal Impedance, θJA 51.5°C/W (0 lfpm)
StorageTemperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
3.3
3.3
70
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.135
3.135
V
mA
mA
mA
IDDA
IDDO
6
27
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VDD + 0.3
V
V
Input Low Voltage
-0.3
0.8
5
Input High Current OE, M1:0, N1:0
Input Low Current OE, M1:0, N1:0
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDD = VIN = 3.465V
µA
µA
V
IIL
VDD = 3.465V, VIN = 0V
-150
2.6
VOH
VOL
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
Mode of Oscillation
Frequency
15.3125
42.67
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
840001AK-34
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REV. A MAY 6, 2005
3
PRELIMINARY
ICS840001-34
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
100
MHz
MHz
fOUT
Output Frequency
106.25
100MHz, Integration Range:
637kHz to 10MHz
106.25MHz, Integration Range:
637kHz to 10MHz
0.54
0.38
ps
ps
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
470
50
ps
ꢀ
All parameters are characterized @ 100MHz and 106.25MHz.
NOTE 1: Please refer to the Phase Noise Plot.
840001-34AK
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REV. A MAY 6, 2005
4
PRELIMINARY
ICS840001-34
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
Phase Noise Plot
SCOPE
VDD,
VDDA,
VDDO
Phase Noise Mask
Qx
LVCMOS
GND
Offset Frequency
f1
f2
-1.65V 5ꢀ
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
VDD
80ꢀ
tF
80ꢀ
tR
2
Q0
tPW
20ꢀ
20ꢀ
tPERIOD
Clock
Outputs
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
840001AK-34
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REV. A MAY 6, 2005
5
PRELIMINARY
ICS840001-34
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise.The ICS840001-34 provides sepa-
rate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD, VDDA and VDDO should be indi-
vidually connected to the power supply plane through vias, and
bypass capacitors should be used for each pin.To achieve op-
timum jitter performance, power supply isolation is required. Fig-
ure 1 illustrates how a 10Ω resistor along with a 10μF and a
.01μF bypass capacitor should be connected to eachVDDA pin.
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840001-34 has been characterized with 18pF parallel allel resonant crystal and were chosen to minimize the ppm er-
ror.The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 26.5625MHz, 18pF par-
XTAL_OUT
XTAL_IN
C1
33p
X1
18pF Parallel Crystal
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
840001-34AK
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REV. A MAY 6, 2005
6
PRELIMINARY
ICS840001-34
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN
θJA at 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
TRANSISTOR COUNT
The transistor count for ICS840001-34 is: 2805
840001AK-34
www.icst.com/products/hiperclocks.html
REV. A MAY 6, 2005
7
PRELIMINARY
ICS840001-34
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
16
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
NE
D
4
4
3.0
D2
E
0.25
1.25
3.0
E2
L
0.25
0.30
1.25
0.50
Reference Document: JEDEC Publication 95, MO-220
840001-34AK
www.icst.com/products/hiperclocks.html
REV. A MAY 6, 2005
8
PRELIMINARY
ICS840001-34
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS840001AK-34
ICS840001AK-34
Marking
1A34
Package
Shipping Packaging
tray
Temperature
0°C to 70°C
0°C to 70°C
16 Lead VFQFN
16 Lead VFQFN
1A34
2500 tape & reel
PCI Express™ is a trademark of PCI-SIG Corporation. All trademarks mentioned are the property of their respective owners.
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
840001AK-34
www.icst.com/products/hiperclocks.html
REV. A MAY 6, 2005
9
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