ICS84025 [ICSI]
CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER; CRYSTAL - TO- LVCMOS / LVTTL频率，扇出缓冲器SYNTHESIZER
| 型号： | ICS84025 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER |
| 文件： | 总12页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS84025
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS84025 is a Crystal-to-LVCMOS/LVTTL • 6 LVCMOS/LVTTLoutputs
Frequency Synthesizer with Fanout Buffer and
a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
VCO frequency is programmed in steps equal
• Crystal oscillator interface
HiPerClockS™
• Output frequency range: 53.125MHz to 125MHz
• Crystal input frequency: 25MHz and 25.5MHz
to the value of the crystal frequency. The VCO and
output frequency can be programmed using the feedback and
output frequency select pins. The low phase noise character-
istics of the ICS84025 make it an ideal clock source for Fibre
Channel 1 and Gigabit Ethernet applications.
• RMS phase jitter at 106.25, using a 25.5MHz crystal
(637KHz to 10MHz): 3.25ps
• Phase noise:
Offset
Noise Power
100Hz ................. -100 dBc/Hz
1KHz ................. -115 dBc/Hz
10KHz ................. -125 dBc/Hz
100KHz ................. -127 dBc/Hz
FUNCTION TABLE
Inputs
XTAL
Output Frequency
F_OUT
MR F_SEL1 F_SEL0
• 3.3V core, outputs may either be 3.3V, 2.5V or 1.8V
• 0°C to 70°C ambient operating temperature
1
0
0
0
0
X
0
0
1
1
X
0
1
0
1
LOW
25.5MHz
25.5MHz
25MHz
53.125MHz
106.25MHz
62.5MHz
• Industrial temperature information available upon request
25MHz
125MHz
BLOCK DIAGRAM
PIN ASSIGNMENT
VDDO
Q0
GND
Q1
VDDO
Q2
GND
Q3
VDDO
Q4
GND
Q5
1
2
3
4
24
23
22
21
20
19
18
F_SEL0
F_SEL1
MR
XTAL1
XTAL2
GND
VDDA
VDD
PLL_SEL
GND
XTAL1
OSC
XTAL2
0
Output
Divider
6
/
5
6
Q0:Q5
1
7
PLL
8
9
10
11
12
17
16
15
14
13
nc
VDDO
Feedback
Divider
ICS84025
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
Top View
F_SEL1
PLL_SEL MR F_SEL0
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84025EM
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REV. A APRIL 16, 2003
1
PRELIMINARY
ICS84025
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDDO
Q0
Type
Description
1, 5, 9, 13
Power
Output
Power
Output
Output
Output
Output
Output
Output supply pins.
2
Clock output. LVCMOS/LVTTL interface levels.
Power supply ground.
3, 7, 11, 15, 19
GND
Q1
4
6
Clock output. LVCMOS/LVTTL interface levels.
Clock output. LVCMOS/LVTTL interface levels.
Clock output. LVCMOS/LVTTL interface levels.
Clock output. LVCMOS/LVTTL interface levels.
Clock output. LVCMOS/LVTTL interface levels.
No connect.
Q2
8
Q3
10
12
14
Q4
Q5
nc
Unused
Selects between the PLL and crystal inputs as the input
to the dividers. When HIGH, selects PLL. When LOW,
selects XTAL1, XTAL2. LVCMOS / LVTTL interface levels.
16
PLL_SEL
Input
Pullup
17
18
VDD
VDDA
Power
Power
Input
Core supply pin.
Analog supply pin.
20, 21
XTAL2, XTAL1
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Active HIGH Master Reset. When logic HIGH, the internal dividers
are reset causing the outputs to go low. When logic LOW, the
internal dividers and the outputs are enabled.
22
MR
Input
Pulldown
LVCMOS / LVTTL interface levels.
23
24
F_SEL1
F_SEL0
Input
Input
Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels.
Pullup Output frequency select pin. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
pF
pF
pF
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
VDD, VDDO = 3.465V
TBD
TBD
TBD
Power Dissipation Capacitance
(per output)
CPD
VDD = 3.465V, VDDO = 2.625V
VDD = 3.465V, VDDO = 1.95V
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REV. A APRIL 16, 2003
2
PRELIMINARY
ICS84025
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VI
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA 46.2°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
3.135
3.135
2.375
1.65
Typical
3.3
3.3
3.3
2.5
1.8
71
Maximum Units
VDD
Core Supply Voltage
3.465
3.465
3.465
2.625
1.95
V
V
VDDA
Analog Supply Voltage
Output Supply Voltage
V
VDDO
V
V
IDD
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
IDDA
IDDO
15
70
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V ± 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
PLL_SEL, MR,
F_SEL0, F_SEL1
PLL_SEL, MR,
F_SEL0, F_SEL1
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
Input High Current
-0.3
MR, F_SEL1
V
DD = VIN = 3.465V
150
5
µA
µA
µA
µA
V
IIH
PLL_SEL, F_SEL0
MR, F_SEL1
VDD = VIN = 3.465V
V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-5
-150
IIL
Input Low Current
PLL_SEL, F_SEL0
V
V
DDO = 3.3V ± 5%
DDO = 2.5V ± 5%
2.6
VOH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
1.8
V
VDDO = 1.8V ± 0.15V
VDDO = 3.3V ± 5%
VDDO- 0.45
V
0.5
0.5
V
VOL
V
DDO = 2.5V ± 5%
V
V
DDO = 1.8V ± 0.15V
0.45
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section,
"Output Load Test Circuit" diagrams.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Fundamental
Units
Mode of Oscillation
Frequency
25
25.5
70
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
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PRELIMINARY
ICS84025
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
MHz
ps
FOUT
tjit(cc)
tsk(o)
tR / tF
odc
Output Frequency
53.125
125
Cycle-to-Cycle Jitter; NOTE 2
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
50
TBD
ps
20% to 80%
300
700
ps
50
%
tPW
Output Pulse Width
tPERIOD/2 - TBD
tPERIOD/2 + TBD
1
ps
tLOCK
PLL Lock Time
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
MHz
ps
FOUT
tjit(cc)
tsk(o)
tR / tF
odc
Output Frequency
53.125
125
Cycle-to-Cycle Jitter; NOTE 2
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
30
TBD
ps
20% to 80%
300
700
ps
50
%
tPW
Output Pulse Width
tPERIOD/2 - TBD
tPERIOD/2 + TBD
1
ps
tLOCK
PLL Lock Time
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ± 0.15V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
MHz
ps
FOUT
tjit(cc)
tsk(o)
tR / tF
odc
Output Frequency
53.125
125
Cycle-to-Cycle Jitter; NOTE 2
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
30
TBD
ps
20% to 80%
300
700
ps
50
%
tPW
Output Pulse Width
tPERIOD/2 - TBD
tPERIOD/2 + TBD
1
ps
tLOCK
PLL Lock Time
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
84025EM
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REV. A APRIL 16, 2003
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PRELIMINARY
ICS84025
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TYPICAL PHASE NOISE
0
25MHz Input
RMS Phase Noise Jitter
12K to 20MHz = 3.5ps (typical)
-10
-20
-30
-40
-50
-60
125MHz
62.5MHz
-70
-80
-90
-100
-110
-120
-130
-140
-150
10
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (HZ)
0
25.5MHz Input
-10
RMS Phase Noise Jitter
12K to 20MHz = 3.5ps (typical)
-20
-30
-40
-50
-60
106.25MHz
53.125MHz
-70
-80
-90
-100
-110
-120
-130
-140
-150
10
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (HZ)
84025EM
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REV. A APRIL 16, 2003
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PRELIMINARY
ICS84025
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VDD, VDDA, VDDO = 1.65V±5%
2.05V±5% 1.25V±5%
SCOPE
SCOPE
VDD
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND = -1.65V±5%
GND = -1.25V±5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
0.9V±0.075V
2.4±0.9V
VDDO
SCOPE
VDD
Qx
Qy
2
VDDO
Qx
LVCMOS
VDDO
2
tsk(o)
GND = -0.9V±0.075V
3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
VOH
VDDO
2
VDDO
2
VDDO
VREF
2
Q0:Q5
➤
➤
tcycle n
tcycle n+1
➤
➤
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
Cycle-to-Cycle Jitter
Period Jitter
VDDO
2
80%
80%
Q0:Q5
Pulse Width
tPERIOD
20%
20%
Clock Outputs
t
t
F
R
tPW
odc =
tPERIOD
odc, tPW & tPERIOD
OUTPUT RISE/FALL TIME
84025EM
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REV. A APRIL 16, 2003
6
PRELIMINARY
ICS84025
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84025 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 24Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VDDA pin.
3.3V
VDD
.01µF
.01µF
24Ω
VDDA
10 µF
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel frequencies with accuracy suitable for most applications.
mode operation. The ICS84025 has a built-in crystal oscillator Additional accuracy can be achieved by adding two small
circuit. This interface can accept either a series or parallel capacitors C1 and C2 as shown in Figure 3.
crystal without additional components and generate
20
XTAL2
C1
18pF
25MHz
X1
21
XTAL1
C2
22pF
ICS84025
Figure 3. CRYSTAL INPUt INTERFACE
84025EM
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REV. A APRIL 16, 2003
7
PRELIMINARY
ICS84025
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
SCHEMATIC EXAMPLE
recommended to have one decouple capacitor per power pin.
Each decoupling capacitor should be located as close as pos-
sible to the power pin. The low pass filter R7, C11 and C16 for
clean analog supply should also be located as close to the VDDA
pin as possible.
Figure 4A shows a schematic example of using an ICS84025. In
this example, the input is a 25MHz parallel resonant crystal with
load capacitor CL=18pF. The frequency fine tuning capacitors
C1 and C2 is 22pF and 18pF respectively. This example also
shows logic control input handling. The configuration is set at
F_SEL[1:0]=11 therefore the output frequency is 125MHz. It is
VDD
VDD
U1
Zo = 50
R6
13
12
VDDO
NC
GND
PLL_SEL
VDD
VDDA
GND
XTAL2
XTAL1
MR
F_SEL1
F_SEL0
Q5
11
R7
10
14
15
16
17
18
19
20
21
22
23
24
GND
10
9
8
7
6
5
4
3
2
43
Q4
VDDO
Q3
GND
Q2
VDDO
Q1
GND
Q0
PLL_SEL
VDDA
22p
C11
0.1u
C16
10u
C1
X1
F_SEL1
F_SEL0
Zo = 50
25MHz,18pF
1
R1
43
VDDO
C2
18p
ICS84025
VDD
RU2
1K
RU3
1K
RU4
1K
SP = Spare, Not Installed
VDD=3.3V
PLL_SEL
F_SEL1
F_SEL0
VDD
(U1,1)
(U1,5)
(U1,9)
(U1,13)
(U1,17)
C6
0.1u
C5
0.1u
C3
0.1u
C4
0.1u
C7
0.1u
RD2
SP
RD3
SP
RD4
SP
FIGURE 4A. ICS84025 SCHEMATIC EXAMPLE
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REV. A APRIL 16, 2003
8
PRELIMINARY
ICS84025
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
• The differential 50Ω output traces should have the
same length.
The following component footprints are used in this layout
example:
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred. This can reduce unwanted in-
ductance between the decoupling capacitor and the power pin
caused by the via.
• Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
• Make sure no other signal traces are routed between the
clock trace pair.
CLOCK TRACES AND TERMINATION
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
21 (XTAL1) and 20 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
C4
R6
50 Ohm traces
GND
VDD
R5
50 Ohm traces
R7
VIA
C3
50 Ohm traces
C16
R4
C1
C11
C7
R3
50 Ohm traces
VDDA
C5
X1
50 Ohm traces
R2
R1
50 Ohm traces
C2
C6
PIN1
U1
FIGURE 4B. PCB BOARD LAYOUT FOR ICS84025
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REV. A APRIL 16, 2003
9
PRELIMINARY
ICS84025
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84025 is: 2949
84025EM
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REV. A APRIL 16, 2003
10
PRELIMINARY
ICS84025
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX
TABLE 7. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
24
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
15.20
7.40
2.55
0.51
0.32
15.85
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119
84025EM
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REV. A APRIL 16, 2003
11
PRELIMINARY
ICS84025
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS84025EM
Marking
Package
24 Lead SOIC
Count
30 per tube
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS84025EM
ICS84025EM
ICS84025EMT
24 Lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
84025EM
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REV. A APRIL 16, 2003
12
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