ICS8430-61 [ICSI]
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER; 500MHZ ，水晶- TO- 3.3V的差分LVPECL频率合成器
| 型号： | ICS8430-61 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总15页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8430-61
Integrated
Circuit
Systems, Inc.
500MH
Z
, CRYSTAL
-
TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY
SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8430-61 is a general purpose, dual output • Dual differential 3.3V LVPECL outputs
ICS
Crystal-to-3.3V Differential LVPECL High Fre-
quency Synthesizer and a member of the
or LVCMOS/LVTTLTEST_CLK
• Selectable crystal oscillator interface
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS.The ICS8430-61 has a select-
• Output frequency range: 20.83MHz to 500MHz
• Crystal input frequency range: 14MHz to 27MHz
• VCO range: 250MHz to 500MHz
able TEST_CLK or crystal inputs. The VCO operates at a fre-
quency range of 250MHz to 500MHz. The VCO frequency is
programmed in steps equal to the value of the input reference
or crystal frequency. The VCO and output frequency can be
programmed using the serial or parallel interfaces to the con-
figuration logic. Frequency steps as small as 1MHz can be
achieved using a 16MHz crystal or TEST_CLK.
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter: 6ps (maximum)
• Cycle-to-cycle jitter: 30ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
XTAL_SEL
TEST_CLK
0
32 31 30 29 28 27 26 25
XTAL_IN
1
OSC
M5
M6
M7
M8
N0
N1
N2
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL_IN
TEST_CLK
XTAL_SEL
VCCA
XTAL_OUT
÷ 16
÷1
ICS8430-61
÷1.5
S_LOAD
S_DATA
S_CLOCK
MR
PLL
÷2
÷3
PHASE DETECTOR
÷4
÷6
0
1
VEE
VCO
÷8
FOUT0
nFOUT0
FOUT1
nFOUT1
MR
÷12
9
10 11 12 13 14 15 16
÷ M
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
M0:M8
N0:N2
Y Package
TopView
8430AY-61
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
1
ICS8430-61
Integrated
Circuit
Systems, Inc.
500MH
Z
, CRYSTAL
-
TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY
SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op- specific default state that will automatically occur during
eration using a 16MHz crystal. Valid PLL loop divider values power-up. The TEST output is LOW when operating in the
for different crystal or input frequencies are defined in the In- parallel input mode. The relationship between the VCO fre-
put Frequency Characteristics, Table 5, NOTE 1.
quency, the crystal frequency and the M divider is defined as
fxtal
16
follows:
x
fVCO =
M
The ICS8430-61 features a fully integrated PLL and therefore
requires no external components for setting the loop band- The M value and the required values of M0 through M8 are
width. A parallel-resonant, fundamental crystal is used as the shown in Table 3B, Programmable VCO Frequency Function
input to the on-chip oscillator. The output of the oscillator is Table.Valid M values for which the PLL will achieve lock for a
divided by 16 prior to the phase detector.With a 16MHz crys- 16MHz reference are defined as 250 ≤ M ≤ 500.The frequency
fVCO fxtal
M
N
tal, this provides a 1MHz reference frequency. The VCO of out is defined as follows:
the PLL operates over a range of 250MHz to 500MHz. The
fout
x
=
=
N
16
output of the M divider is also applied to the phase detector.
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
The phase detector and the M divider force the VCO output bits with the rising edge of S_CLOCK. The contents of the
frequency to be M times the reference frequency by adjusting shift register are loaded into the M divider and N output di-
the VCO control voltage. Note that for some values of M (ei- vider when S_LOAD transitions from LOW-to-HIGH. The M
ther too high or too low), the PLL will not achieve lock. The divide and N output divide values are latched on the HIGH-to-
output of the VCO is scaled by a divider prior to being sent to LOW transition of S_LOAD. If S_LOAD is held HIGH, data at
each of the LVPECL output buffers. The divider provides a the S_DATA input is passed directly to the M divider and N
50% output duty cycle.
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
The programmable features of the ICS8430-61 support two T1 andT0.The internal registers T0 andT1 determine the state
input modes and to program the M divider and N output di- of the TEST output as follows:
vider.The two input operational modes are parallel and serial.
Figure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW.The data on inputs
T1 T0
TEST Output
LOW
M0 through M8 and N0 through N2 is passed directly to the M
divider and N output divider. On the LOW-to-HIGH transition
of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and N bits can
be hard-wired to set the M divider and N output divider to a
0
0
1
1
0
1
0
1
S_Data, Shift Register Input
Output of M divider
CMOS Fout
SERIAL
L
OADING
S_CLOCK
S_DATA
S_LOAD
T1
T0
N2
N1
N0
M8 M7 M6 M5 M4 M3 M2 M1 M0
t
t
H
S
nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N2
nP_LOAD
M, N
t
t
H
Time
S
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
8430AY-61
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
2
ICS8430-61
Integrated
Circuit
Systems, Inc.
500MH
Z
, CRYSTAL
-
TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY
SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
28, 29, 30
31, 32, 1, 2 M3, M4, M5, M6
M0, M1, M2
Input Pulldown
M divider inputs. Data latched on LOW-to-HIGH transition of
nP_LOAD input. LVCMOS / LVTTL interface levels.
3, 4
M7, M8
Input
Pullup
5, 7
6
N0, N2
N1
Input Pulldown
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
Input
Pullup
8, 16
VEE
Power
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS interface levels.
9
TEST
VCC
Output
Power
10
Core supply pin.
11, 12
13
FOUT1, nFOUT1 Output
VCCO Power
FOUT0, nFOUT0 Output
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Output supply pin.
14, 15
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inverted
17
MR
Input Pulldown outputs nFOUTx to go high. When Logic LOW, the internal dividers
and the outputs are enabled. Assertion of MR does not affect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS / LVTTL interface levels.
18
19
S_CLOCK
S_DATA
Input Pulldown
Input Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
20
21
S_LOAD
VCCA
Input Pulldown
Power
Input
Analog supply pin.
Selects between crystal oscillator or test inputs as the PLL
reference source. Selects XTAL inputs when HIGH. Selects
TEST_CLK when LOW. LVCMOS / LVTTL interface levels.
22
23
XTAL_SEL
TEST_CLK
Pullup
Input Pulldown Test clock input. LVCMOS / LVTTL interface levels.
24,
25
XTAL_IN,
XTAL_OUT
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Input
Parallel load input. Determines when data present at M8:M0 is
Input Pulldown loaded into M divider, and when data present at N2:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
26
nP_LOAD
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
27
VCO_SEL
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
8430AY-61
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
3
ICS8430-61
Integrated
Circuit
Systems, Inc.
500MH
Z
, CRYSTAL
-
TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY
SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
L
Data Data
Data Data
X
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
L
L
L
↑
L
L
↑
X
↑
L
X
H
H
X
X
X
X
Data
Data
L
L
L
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
256
M8
0
128
M7
1
64
M6
1
32
M5
1
16
M4
1
8
M3
1
4
M2
0
2
M1
1
1
M0
0
VCO Frequency
(MHz)
M Divide
250
251
252
253
•
250
251
252
253
•
0
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
498
499
500
498
499
500
1
1
1
1
1
0
0
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
0
0
NOTE 1: These M divide values and the resulting frequencies correspond to a TEST_CLK or crystal frequency of 16MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Frequency (MHz)
N Divider Value
N2
0
N1
0
N0
0
Minimum
250
Maximum
500
1
1.5
2
0
0
1
166.66
125
333.33
250
0
1
0
0
1
1
3
83.33
62.5
166.66
125
1
0
0
4
1
0
1
6
41.66
31.25
20.83
83.33
62.5
1
1
0
8
1
1
1
12
41.66
8430AY-61
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
4
ICS8430-61
Integrated
Circuit
Systems, Inc.
500MH
Z
, CRYSTAL
-
TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY
SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
47.9°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.465
3.465
3.465
155
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
3.135
3.3
V
mA
mA
ICCA
55
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Minimu-
Symbol Parameter
Test Conditions
Typical Maximum Units
m
M0:M8, N0:N2, MR,
S_LOAD, S_DATA,
S_CLOCK, nP_LOAD,
VCO_SEL, XTAL_SEL
2
V
CC + 0.3
V
V
V
Input
VIH
High Voltage
TEST_CLK
2
VCC + 0.3
0.8
M0:M8, N0:N2, MR,
S_LOAD, S_DATA,
S_CLOCK, nP_LOAD,
VCO_SEL, XTAL_SEL
-0.3
-0.3
Input
VIL
Low Voltage
TEST_CLK
1.3
150
5
V
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
VCC = VIN = 3.465V
VCC = VIN = 3.465V
µA
µA
µA
Input
IIH
High Current
M5, XTAL_SEL, VCO_SEL
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
VCC = 3.465V,
VIN = 0V
-5
Input
IIL
Low Current
VCC = 3.465V,
VIN = 0V
M5, XTAL_SEL, VCO_SEL
TEST; NOTE 1
-150
2.6
µA
V
Output
VOH
High Voltage
Output
VOL
TEST; NOTE 1
0.5
V
Low Voltage
NOTE 1:Outputs terminated with 50Ω toVCCO/2.
8430AY-61
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
5
ICS8430-61
Integrated
Circuit
Systems, Inc.
500MH
Z
, CRYSTAL
-
TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY
SYNTHESIZER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. See "Parameter Measurement Information" section,
"3.3V Output Load Test Circuit" figure.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK; NOTE 1
XTAL_IN XTAL_OUT NOTE 1
S_CLOCK
14
14
27
27
50
MHz
MHz
MHz
Input
fIN
Frequency
NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within
the 250MHz to 500MHz range. Using the minimum input frequency of 14MHz, valid values of M are 286 ≤ M ≤ 511.
Using the maximum input frequency of 27MHz, valid values of M are 149 ≤ M ≤ 296.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
14
27
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
20.83
500
30
MHz
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
%
N ≠ 1.5
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 4
N = 1.5
100
6
tjit(per)
tsk(o)
tR / tF
Period Jitter, RMS; NOTE 1, 3
Output Skew; NOTE 2, 4
Output Rise/Fall Time
15
20% to 80%
200
5
700
M, N to nP_LOAD
tS
Setup Time
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
5
5
tH
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
Even N divides
Odd N divides
48
45
52
55
1
odc
Output Duty Cycle
PLL Lock Time
%
tLOCK
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: N divide = 1.5 characterized using the Wavecrest tailfit algorithm.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8430AY-61
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
6
ICS8430-61
Integrated
Circuit
Systems, Inc.
500MH
Z
, CRYSTAL
-
TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY
SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
SCOPE
nFOUTx
FOUTx
VCC
VCCA, VCCO
,
Qx
LVPECL
nFOUTy
FOUTy
nQx
VEE
tsk(o)
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
VOH
VREF
nFOUTx
FOUTx
➤
➤
tcycle n
tcycle n+1
➤
➤
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
t
jit(cc) =
tcycle n –tcycle n+1
1000 Cycles
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
PERIOD JITTER
CYCLE
-
TO-CYCLE
JITTER
nFOUTx
FOUTx
80%
80%
VSWING
20%
Pulse Width
Clock
20%
tPERIOD
Outputs
tF
tR
tPW
odc =
tPERIOD
O
UTPUT
R
ISE/FALL
T
IME
O
UTPUT
D
UTY
CYCLE/PULSE WIDTH/PERIOD
8430AY-61
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
7
ICS8430-61
Integrated
Circuit
Systems, Inc.
500MH
Z
, CRYSTAL
-
TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY
SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8430-61 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10 µF
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- drive 50Ω transmission lines. Matched impedance techniques
tion for LVPECL outputs.The two different layouts mentioned should be used to maximize operating frequency and mini-
are recommended only as guidelines.
mize signal distortion. There are a few simple termination
schemes. Figures 3A and 3B show two different layouts which
FOUT and nFOUT are low impedance follower outputs that are recommended only as guidelines. Other suitable clock lay-
generate ECL/LVPECL compatible outputs.Therefore, termi- outs may exist and it would be recommended that the board
nating resistors (DC current path to ground) or current sources designers simulate to guarantee compatibility across all printed
must be used for functionality.These outputs are designed to circuit and clock component process variations.
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
8430AY-61
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
8
ICS8430-61
Integrated
Circuit
Systems, Inc.
500MH
Z
, CRYSTAL
-
TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY
SYNTHESIZER
CRYSTAL INPUT INTERFACE
The ICS8430-61 has been characterized with 18pF parallel error. These same capacitor values will tune any 18pF paral-
resonant crystals. The capacitor values, C1 and C2, shown lel resonant crystal over the frequency range and other pa-
in Figure 4 below were determined using a 25MHz, 18pF par- rameters specified in this data sheet.The optimum C1 and C2
allel resonant crystal and were chosen to minimize the ppm values can be slightly adjusted for different board layouts.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
ICS8430-61
Figure 4. CRYSTAL INPUt INTERFACE
LAYOUT GUIDELINE
The schematic of the ICS8430-61 layout example used in this The layout in the actual system will depend on the selected
layout guideline is shown in Figure 5A. The ICS8430-61 rec- component types, the density of the components, the density
ommended PCB board layout for this example is shown in of the traces, and the stack up of the P.C. board.
Figure 5B. This layout example is used as a general guideline.
C1
C2
X1
U1
VCC
1
24
R7
10
M5
M6
M7
M8
N0
N1
N2
VEE
XTAL_IN
REF_IN
nXTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
REF_IN
XTAL_SEL
2
3
4
5
6
7
8
23
22
21
20
19
18
17
VCCA
S_LOAD
S_DATA
S_CLOCK
C11
C16
10u
0.01u
8430-61
VCC
R1
125
R3
125
Zo = 50 Ohm
IN+
IN-
C14
0.1u
TL1
+
-
C15
0.1u
Zo = 50 Ohm
TL2
R2
84
R4
84
FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT
www.icst.com/products/hiperclocks.html
8430AY-61
REV. A JULY 22, 2004
9
ICS8430-61
Integrated
Circuit
Systems, Inc.
500MH
Z
, CRYSTAL
-
TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY
SYNTHESIZER
• The traces with 50Ω transmission lines TL1 andTL2 at
FOUT and nFOUT should have equal delay and run ad-
jacent to each other.Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
• Keep the clock trace on the same layer.Whenever pos-
sible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
Maximize the pad size of the power (ground) at the decoupling
capacitor.Maximize the number of vias between power (ground)
and the pads.This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
• Make sure no other signal trace is routed between the
clock trace pair.
If VCCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the VCCA pin as possible.
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible. Other
termination schemes can also be used but are not shown in
this example.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality.Poor clock signal
quality can degrade the system performance or cause system fail-
ure. In the synchronous high-speed digital system, the clock signal
is less tolerable to poor signal quality than other signals. Any ring-
ing on the rising or falling edge or excessive ring back can cause
system failure. The trace shape and the trace delay might be re-
stricted by the available space on the board and the component
location.While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL_IN) and 25 (XTAL_OUT).The trace length between the
X1 and U1 should be kept to a minimum to avoid unwanted para-
sitic inductance and capacitance. Other signal traces should not
be routed near the crystal traces.
GND
C1
C2
VCC
X1
VIA
U1
PIN 1
C16
VCCA
C11
R7
Close to the input
pins of the
receiver
R1
R3
R2
R4
C15
TL1
C14
TL1N
TL1, TL21N are 50 Ohm
traces and equal length
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8430-61
www.icst.com/products/hiperclocks.html
8430AY-61
REV. A JULY 22, 2004
10
ICS8430-61
Integrated
Circuit
Systems, Inc.
500MH
Z
, CRYSTAL
-
TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY
SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8430-61.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8430-61 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 155mA = 537.1mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 537.1mW + 60mW = 597.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W perTable 8 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.597W * 42.1°C/W = 95°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
8430AY-61
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
11
ICS8430-61
Integrated
Circuit
Systems, Inc.
500MH
Z
, CRYSTAL
-
TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY
SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
8430AY-61
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
12
ICS8430-61
Integrated
Circuit
Systems, Inc.
500MH
Z
, CRYSTAL
-
TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY
SYNTHESIZER
RELIABILITY INFORMATION
TABLE 9. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8430-61 is: 4258
8430AY-61
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
13
ICS8430-61
Integrated
Circuit
Systems, Inc.
500MH
Z
, CRYSTAL
-
TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY
SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
8430AY-61
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
14
ICS8430-61
Integrated
Circuit
Systems, Inc.
500MH
Z
, CRYSTAL
-
TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY
SYNTHESIZER
TABLE 11. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS8430AY-61
ICS8430AY-61T
ICS8430AY-61
ICS8430AY-61
32 Lead LQFP
32 Lead LQFP on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8430AY-61
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
15
相关型号：
ICS8430-71B
700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICSI
©2020 ICPDF网 联系我们和版权申明