ICS84320AY-01LNT [ICSI]

780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER; 780MHZ ,水晶- TO- 3.3V的差分LVPECL频率合成器
ICS84320AY-01LNT
型号: ICS84320AY-01LNT
厂家: INTEGRATED CIRCUIT SOLUTION INC    INTEGRATED CIRCUIT SOLUTION INC
描述:

780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
780MHZ ,水晶- TO- 3.3V的差分LVPECL频率合成器

晶体 外围集成电路 时钟
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中文:  中文翻译
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ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
The ICS84320-01 is a general purpose, dual out- Dual differential 3.3V LVPECL outputs  
ICS  
put Crystal-to-3.3V Differential LVPECL High Fre-  
quency Synthesizer and a member of the  
or LVCMOS/LVTTLTEST_CLK  
Selectable crystal oscillator interface  
HiPerClockS™  
HiPerClockS™ family of High Performance Clock  
Solutions from ICS. The ICS84320-01 has a se-  
Output frequency range: 77.5MHz to 780MHz  
Crystal input frequency range: 14MHz to 40MHz  
VCO range: 620MHz to 780MHz  
lectable TEST_CLK or crystal inputs. The VCO operates at a  
frequency range of 620MHz to 780MHz. The VCO frequency  
is programmed in steps equal to the value of the input refer-  
ence or crystal frequency. The VCO and output frequency  
can be programmed using the serial or parallel interfaces to  
the configuration logic. The low phase noise characteristics  
of the ICS84320-01 make it an ideal clock source for 10 Gigabit  
Ethernet, SONET, and Serial Attached SCSI applications.  
Parallel or serial interface for programming counter  
and output dividers  
Duty cycle: 49% - 51% (N > 1)  
RMS period jitter: 2.0ps (typical)  
RMS phase jitter at 155.52MHz, using a 38.88MHz crystal  
(12KHz to 20MHz): 2.5ps (typical)  
Phase noise: 155.52MHz (typical), using a 38.88MHz crystal  
Offset  
Noise Power  
100Hz ..................-90.5 dBc/Hz  
1KHz ................ -114.2 dBc/Hz  
10KHz ................ -123.6 dBc/Hz  
100KHz ................ -128.1 dBc/Hz  
3.3V supply voltage  
Lead-Free/Annealed package available  
0°C to 70°C ambient operating temperature  
BLOCK DIAGRAM  
VCO_SEL  
PIN ASSIGNMENT  
XTAL_SEL  
TEST_CLK  
0
32 31 30 29 28 27 26 25  
XTAL1  
1
M5  
M6  
M7  
M8  
N0  
N1  
nc  
OSC  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
XTAL2  
XTAL2  
TEST_CLK  
XTAL_SEL  
VCCA  
ICS84320-01  
10 11 12 13 14 15 16  
32-Lead LQFP  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
PLL  
÷ N  
PHASE DETECTOR  
÷ 1  
÷ 2  
÷ 4  
÷ 8  
MR  
0
1
VEE  
VCO  
FOUT0  
nFOUT0  
FOUT1  
nFOUT1  
9
÷ M  
S_LOAD  
S_DATA  
S_CLOCK  
nP_LOAD  
CONFIGURATION  
INTERFACE  
LOGIC  
TEST  
7mm x 7mm x 1.4mm package body  
Y Package  
TopView  
M0:M8  
N0:N1  
84320AY-01  
www.icst.com/products/hiperclocks.html  
REV. A AUGUST 24, 2004  
1
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
FUNCTIONAL DESCRIPTION  
NOTE: The functional description that follows describes op- matically occur during power-up.TheTEST output is LOW when  
eration using a 25MHz crystal. Valid PLL loop divider values operating in the parallel input mode.The relation-ship between  
for different crystal or input frequencies are defined in the In- the VCO frequency, the crystal frequency and the M divider is  
put Frequency Characteristics, Table 5, NOTE 1.  
defined as follows:  
fVCO = fxtal x M  
The ICS84320-01 features a fully integrated PLL and there-  
fore requires no external components for setting the loop band- The M value and the required values of M0 through M8 are  
width. A fundamental crystal is used as the input to the on- shown in Table 3B to program the VCO Frequency Function  
chip oscillator.The output of the oscillator is fed into the phase Table.Valid M values for which the PLL will achieve lock for a  
detector. A 25MHz crystal provides a 25MHz phase detector 25MHz reference are defined as 25 M 31.The frequency  
reference frequency. The VCO of the PLL operates over a out is defined as follows:  
range of 620MHz to 780MHz. The output of the M divider is  
also applied to the phase detector.  
FOUT = fVCO = fxtal x M  
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD  
The phase detector and the M divider force the VCO output fre- is LOW. The shift register is loaded by sampling the S_DATA  
quency to be M times the reference frequency by adjusting the bits with the rising edge of S_CLOCK. The contents of the  
VCO control voltage. Note that for some values of M (either too shift register are loaded into the M divider and N output di-  
high or too low), the PLL will not achieve lock. The output of the vider when S_LOAD transitions from LOW-to-HIGH. The M  
VCO is scaled by a divider prior to being sent to each of the LVPECL divide and N output divide values are latched on the HIGH-to-  
output buffers.The divider provides a 50% output duty cycle.  
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at  
the S_DATA input is passed directly to the M divider and N  
The programmable features of the ICS84320-01 support two output divider on each rising edge of S_CLOCK. The serial  
input modes to program the M divider and N output divider. The mode can be used to program the M and N bits and test bits  
two input operational modes are parallel and serial. Figure 1 shows T1 andT0.The internal registers T0 andT1 determine the state  
the timing diagram for each mode. In parallel mode, the nP_LOAD of the TEST output as follows:  
input is initially LOW. The data on inputs M0 through M8 and N0  
T1 T0  
TEST Output  
LOW  
and N1 is passed directly to the M divider and N output divider.  
On the LOW-to-HIGH transition of the nP_LOAD input, the data  
is latched and the M divider remains loaded until the next  
LOW transition on nP_LOAD or until a serial event occurs. As a  
result, the M and N bits can be hardwired to set the M divider  
and N output divider to a specific default state that will auto-  
0
0
1
1
0
1
0
1
S_Data, Shift Register Input  
Output of M divider  
CMOS Fout  
S
ERIAL  
LOADING  
S_CLOCK  
S_DATA  
S_LOAD  
T 1  
T0  
*
NULL N1  
N0  
M8  
M7  
M6  
M5  
M4 M3  
M2  
M1  
M0  
t
t
H
S
nP_LOAD  
t
S
P
ARALLEL LOADING  
M0:M8, N0:N1  
nP_LOAD  
M, N  
t
t
H
Time  
S
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS  
*NOTE: The NULL timing slot must be observed.  
84320AY-01  
www.icst.com/products/hiperclocks.html  
REV. A AUGUST 24, 2004  
2
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
TABLE 1. PIN DESCRIPTIONS  
Number  
Name  
Type  
Pullup  
Description  
1
M5  
Input  
Input  
M divider inputs. Data latched on LOW-to-HIGH transition of  
nP_LOAD input. LVCMOS / LVTTL interface levels.  
2, 3, 4,  
28, 29,  
30, 31, 32  
M6, M7, M8,  
M0, M1,  
M2, M3, M4  
Pulldown  
Pulldown  
Determines output divider value as defined in Table 3C,  
Function Table. LVCMOS / LVTTL interface levels.  
5, 6  
N0, N1  
Input  
7
nc  
Unused  
Power  
No connect.  
8, 16  
VEE  
Negative supply pins.  
Test output which is ACTIVE in the serial mode of operation.  
Output driven LOW in parallel mode.  
LVCMOS/LVTTL interface levels.  
9
TEST  
VCC  
Output  
Power  
10  
Core supply pin.  
11, 12  
13  
FOUT1, nFOUT1 Output  
VCCO Power  
FOUT0, nFOUT0 Output  
Differential output for the synthesizer. LVPECL interface levels.  
Output supply pin.  
14, 15  
Differential output for the synthesizer. LVPECL interface levels.  
Active High Master Reset. When logic HIGH, forces the internal  
dividers are reset causing the true outputs FOUTx to go low and the  
17  
MR  
Input  
Pulldown inverted outputs nFOUTx to go high. When logic LOW, the internal  
dividers and the outputs are enabled. Assertion of MR does not  
affect loaded M, N, and T values. LVCMOS / LVTTL interface levels.  
Clocks in serial data present at S_DATA input into the shift register  
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.  
Shift register serial input. Data sampled on the rising edge of  
S_CLOCK. LVCMOS/LVTTL interface levels.  
18  
19  
S_CLOCK  
S_DATA  
Input  
Input  
Pulldown  
Pulldown  
Controls transition of data from shift register into the dividers.  
LVCMOS / LVTTL interface levels.  
20  
21  
S_LOAD  
VCCA  
Input  
Pulldown  
Power  
Analog supply pin.  
Selects between crystal or test inputs as the PLL reference source.  
22  
XTAL_SEL  
Input  
Pullup  
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.  
LVCMOS / LVTTL interface levels.  
23  
TEST_CLK  
Input  
Input  
Pulldown Test clock input. LVCMOS / LVTTL interface levels.  
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.  
24, 25  
XTAL2, XTAL1  
Parallel load input. Determines when data present at M8:M0 is  
Pulldown loaded into M divider, and when data present at N1:N0 sets the  
N output divider value. LVCMOS / LVTTL interface levels.  
26  
nP_LOAD  
Input  
Determines whether synthesizer is in PLL or bypass mode.  
LVCMOS / LVTTL interface levels.  
27  
VCO_SEL  
Input  
Pullup  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
TABLE 2. PIN CHARACTERISTICS  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum Typical Maximum Units  
Input Capacitance  
Input Pullup Resistor  
4
pF  
KΩ  
KΩ  
RPULLUP  
51  
51  
RPULLDOWN Input Pulldown Resistor  
84320AY-01  
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REV. A AUGUST 24, 2004  
3
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE  
Inputs  
Conditions  
MR nP_LOAD  
M
N
S_LOAD S_CLOCK S_DATA  
H
X
X
X
X
X
X
Reset. Forces outputs LOW.  
Data on M and N inputs passed directly to the M  
divider and N output divider. TEST output forced LOW.  
L
L
Data Data  
Data Data  
X
X
X
Data is latched into input registers and remains loaded  
until next LOW transition or until a serial event occurs.  
Serial input mode. Shift register is loaded with data on  
S_DATA on each rising edge of S_CLOCK.  
Contents of the shift register are passed to the  
M divider and N output divider.  
L
L
L
L
L
X
L
X
H
H
X
X
X
X
Data  
Data  
L
L
L
H
H
H
X
X
X
X
X
X
L
L
X
Data  
X
M divider and N output divider values are latched.  
Parallel or serial input do not affect shift registers.  
S_DATA passed directly to M divider as it is clocked.  
H
Data  
NOTE: L = LOW  
H = HIGH  
X = Don't care  
= Rising edge transition  
= Falling edge transition  
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE  
256  
M8  
0
128  
M7  
0
64  
M6  
0
32  
M5  
0
16  
M4  
1
8
M3  
1
4
M2  
0
2
M1  
0
1
M0  
1
VCO Frequency  
(MHz)  
M Divide  
625  
25  
700  
28  
0
0
0
0
1
1
1
0
0
775  
31  
0
0
0
0
1
1
1
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency  
of 25MHz.  
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE  
Inputs  
Output Frequency (MHz)  
N Divider Value  
N1  
N0  
0
Minimum  
620  
Maximum  
780  
0
0
1
1
1
2
4
8
1
310  
390  
0
155  
195  
1
77.5  
97.5  
84320AY-01  
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REV. A AUGUST 24, 2004  
4
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
ABSOLUTE MAXIMUM RATINGS  
SupplyVoltage, V  
4.6V  
NOTE: Stresses beyond those listed under Absolute  
Maximum Ratings may cause permanent damage to the  
device.These ratings are stress specifications only.Functional  
operation of product at these conditions or any conditions be-  
yond those listed in the DC Characteristics or AC Character-  
istics is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect product reliability.  
CC  
Inputs, V  
-0.5V to VCC + 0.5 V  
I
Outputs, VO (LVCMOS)  
-0.5V to VDDO + 0.5V  
Outputs, IO (LVPECL)  
Continuous Current  
Surge Current  
50mA  
100mA  
PackageThermal Impedance, θ  
47.9°C/W (0 lfpm)  
-65°C to 150°C  
JA  
StorageTemperature, T  
STG  
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C  
Symbol Parameter  
Test Conditions  
Minimum  
3.135  
Typical  
3.3  
Maximum Units  
VCC  
VCCA  
VCCO  
IEE  
Core Supply Voltage  
3.465  
3.465  
3.465  
155  
V
V
Analog Supply Voltage  
Output Supply Voltage  
Power Supply Current  
Analog Supply Current  
3.135  
3.3  
3.135  
3.3  
V
mA  
mA  
ICCA  
22  
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C  
Symbol Parameter  
Test Conditions  
Minimum Typical Maximum Units  
VCO_SEL, XTAL_SEL, MR,  
S_LOAD, nP_LOAD, N0:N1,  
S_DATA, S_CLOCK, M0:M8  
2
V
CC + 0.3  
V
V
Input  
VIH  
High Voltage  
TEST_CLK  
2
VCC + 0.3  
0.8  
VCO_SEL, XTAL_SEL, MR,  
S_LOAD, nP_LOAD, N0:N1,  
S_DATA, S_CLOCK, M0:M8  
-0.3  
-0.3  
V
Input  
VIL  
Low Voltage  
TEST_CLK  
1.3  
V
M0-M4, M6-M8, N0, N1, MR,  
S_CLOCK, TEST_CLK,  
S_DATA, S_LOAD, nP_LOAD  
VCC = VIN = 3.465V  
VCC = VIN = 3.465V  
150  
µA  
Input  
IIH  
High Current  
M5, XTAL_SEL, VCO_SEL  
5
µA  
µA  
M0-M4, M6-M8, N0, N1, MR,  
S_CLOCK, TEST_CLK,  
S_DATA, S_LOAD, nP_LOAD  
VCC = 3.465V,  
VIN = 0V  
-5  
Input  
IIL  
Low Current  
VCC = 3.465V,  
VIN = 0V  
M5, XTAL_SEL, VCO_SEL  
TEST; NOTE 1  
-150  
2.6  
µA  
V
Output  
VOH  
High Voltage  
Output  
VOL  
TEST; NOTE 1  
0.5  
V
Low Voltage  
NOTE 1:Outputs terminated with 50toVCCO/2.  
84320AY-01  
www.icst.com/products/hiperclocks.html  
REV. A AUGUST 24, 2004  
5
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C  
Symbol Parameter Test Conditions Minimum Typical Maximum Units  
VOH  
Output High Voltage; NOTE 1  
VCCO - 1.4  
VCCO - 2.0  
0.6  
VCCO - 1.0  
VCCO - 1.7  
1.0  
V
V
V
VOL  
Output Low Voltage; NOTE 1  
VSWING  
Peak-to-Peak Output Voltage Swing  
NOTE 1: Outputs terminated with 50 to VCCO - 2V. See "Parameter Measurement Information" section,  
"3.3V Output Load Test Circuit".  
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C  
Symbol Parameter  
Test Conditions  
Minimum Typical Maximum Units  
TEST_CLK; NOTE 1  
14  
14  
40  
40  
50  
MHz  
MHz  
MHz  
fIN  
Input Frequency XTAL1, XTAL2; NOTE 1  
S_CLOCK  
NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the  
620MHz to780MHz range. Using the minimum input frequency of 14MHz, valid values of M are 45 M 55. Using the  
maximum frequency of 40MHz, valid values of M are 16 M 19.  
TABLE 6. CRYSTAL CHARACTERISTICS  
Parameter  
Test Conditions  
Minimum Typical Maximum  
Units  
Mode of Oscillation  
Frequency  
Fundamental  
14  
40  
50  
7
MHz  
Equivalent Series Resistance (ESR)  
Shunt Capacitance  
pF  
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C  
Symbol Parameter  
Test Conditions  
fOUT > 100MHz  
20% to 80%  
Minimum  
Typical  
Maximum  
780  
Units  
FOUT  
Output Frequency  
77.5  
MHz  
ps  
ps  
ps  
ns  
ns  
ns  
ns  
ns  
ns  
%
tjit(per)  
tsk(o)  
tR / tF  
Period Jitter, RMS; NOTE 1  
Output Skew; NOTE 2, 3  
Output Rise/Fall Time  
2.0  
2.6  
15  
150  
600  
M, N to nP_LOAD  
5
tS  
Setup Time S_DATA to S_CLOCK  
S_CLOCK to S_LOAD  
5
5
M, N to nP_LOAD  
5
tH  
Hold Time  
S_DATA to S_CLOCK  
S_CLOCK to S_LOAD  
5
5
N > 1  
fOUT 625  
ƒ> 625  
49  
45  
51  
55  
odc  
Output Duty Cycle  
%
tPW  
Output Pulse Width  
PLL Lock Time  
tPERIOD/2 - 150  
tPERIOD/2 + 150  
1
ps  
ms  
tLOCK  
See Parameter Measurement Information section.  
NOTE 1: Jitter performance using XTAL inputs.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.  
Measured at the output differential cross points.  
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.  
84320AY-01  
www.icst.com/products/hiperclocks.html  
REV. A AUGUST 24, 2004  
6
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
TYPICAL PHASE NOISE AT 155.52MHZ  
0
-10  
-20  
OC-48 Sonet Bandpass Filter  
-30  
-40  
155.52MHz  
RMS Phase Jitter (Random)  
-50  
12KHz to 20MHz = 2.5ps (typical)  
-60  
Raw Phase Noise Data  
-70  
-80  
-90  
-100  
-110  
-120  
-130  
-140  
-150  
-160  
-170  
-180  
Phase Noise Result by adding  
Sonet Bandpass Filter to raw data  
-190  
10  
100  
1k  
10k  
100k  
1M  
10M  
100M  
OFFSET FREQUENCY (HZ)  
TYPICAL PHASE NOISE AT 622.08MHZ  
0
-10  
-20  
OC-48 Sonet Bandpass Filter  
-30  
-40  
622.08MHz  
-50  
RMS Phase Jitter (Random)  
Raw Phase Noise Data  
-60  
12KHz to 20MHz = 2.48ps (typical)  
-70  
-80  
-90  
-100  
-110  
-120  
-130  
-140  
-150  
-160  
-170  
Phase Noise Result by adding  
Sonet Bandpass Filter to raw data  
-180  
-190  
10  
100  
1k  
10k  
100k  
1M  
10M  
100M  
OFFSET FREQUENCY (HZ)  
84320AY-01  
www.icst.com/products/hiperclocks.html  
REV. A AUGUST 24, 2004  
7
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
PARAMETER MEASUREMENT INFORMATION  
2V  
SCOPE  
nFOUTx  
FOUTx  
VCC  
VCCA  
VCCO  
,
Qx  
,
LVPECL  
nFOUTy  
FOUTy  
nQx  
VEE  
tsk(o)  
-1.3V 0.165V  
3.3V OUTPUT LOAD AC TEST CIRCUIT  
OUTPUT SKEW  
VOH  
VREF  
nFOUTx  
FOUTx  
Pulse Width  
tPERIOD  
VOL  
1σ contains 68.26% of all measurements  
2σ contains 95.4% of all measurements  
3σ contains 99.73% of all measurements  
4σ contains 99.99366% of all measurements  
6σ contains (100-1.973x10-7)% of all measurements  
tPW  
odc =  
tPERIOD  
Histogram  
Reference Point  
(Trigger Edge)  
Mean Period  
(First edge after trigger)  
PERIOD JITTER  
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD  
80%  
80%  
VSWING  
Clock  
20%  
20%  
Outputs  
tF  
tR  
OUTPUT RISE/FALL TIME  
84320AY-01  
www.icst.com/products/hiperclocks.html  
REV. A AUGUST 24, 2004  
8
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
APPLICATION INFORMATION  
POWER SUPPLY FILTERING TECHNIQUES  
As in any high speed analog circuitry, the power supply pins  
are vulnerable to random noise. The ICS84320-01 provides  
separate power supplies to isolate any high switching  
noise from the outputs to the internal PLL.VCC, VCCA, and VCCO  
should be individually connected to the power supply  
plane through vias, and bypass capacitors should be  
used for each pin. To achieve optimum jitter performance,  
power supply isolation is required. Figure 2 illustrates how  
a 24resistor along with a 10µF and a .01µF bypass  
capacitor should be connected to each VCCA pin.  
3.3V  
VCC  
.01µF  
.01µF  
24Ω  
VCCA  
10µF  
FIGURE 2. POWER SUPPLY FILTERING  
CRYSTAL INPUT INTERFACE  
A crystal can be characterized for either series or parallel mode suitable for most applications. Additional accuracy can be  
operation.The ICS84320-01 has a built-in crystal oscillator circuit. achieved by adding two small capacitors C1 and C2 as shown in  
This interface can accept either a series or parallel crystal without Figure 3.  
additional components and generate frequencies with accuracy  
25  
XTAL1  
C1  
18p  
X1  
18pF Parallel Crystal  
24  
XTAL2  
C2  
22p  
ICS84320-01  
Figure 3. CRYSTAL INPUt INTERFACE  
84320AY-01  
www.icst.com/products/hiperclocks.html  
REV. A AUGUST 24, 2004  
9
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
TERMINATION FOR LVPECL OUTPUTS  
The clock layout topology shown below is a typical termina- drive 50transmission lines. Matched impedance techniques  
tion for LVPECL outputs.The two different layouts mentioned should be used to maximize operating frequency and minimize  
are recommended only as guidelines.  
signal distortion. Figures 4A and 4B show two different layouts  
which are recommended only as guidelines. Other suitable clock  
layouts may exist and it would be recommended that the board  
designers simulate to guarantee compatibility across all printed  
circuit and clock component process variations.  
FOUT and nFOUT are low impedance follower outputs that  
generate ECL/LVPECL compatible outputs.Therefore, terminat-  
ing resistors (DC current path to ground) or current sources  
must be used for functionality. These outputs are designed to  
3.3V  
Z
o = 50  
125  
125Ω  
FOUT  
FIN  
Z
o = 50Ω  
Zo = 50Ω  
FOUT  
FIN  
50Ω  
50Ω  
VCC - 2V  
Zo = 50Ω  
1
RTT =  
Zo  
RTT  
((VOH + VOL) / (VCC – 2)) – 2  
84Ω  
84Ω  
FIGURE 4A. LVPECL OUTPUT TERMINATION  
FIGURE 4B. LVPECL OUTPUT TERMINATION  
LAYOUT GUIDELINE  
The schematic of the ICS84320-01 layout example used in  
this layout guideline is shown in Figure 5A. The ICS84320-01  
recommended PCB board layout for this example is shown in  
Figure 5B. This layout example is used as a general guideline.  
The layout in the actual system will depend on the selected  
component types, the density of the components, the density  
of the traces, and the stack up of the P.C. board.  
C1  
C2  
X1  
U1  
VCC  
R7  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
M5  
M6  
M7  
M8  
N0  
N1  
nc  
XTAL2  
T_CLK  
nXTAL_SEL  
VCCA  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
REF_IN  
XTAL_SEL  
24  
VCCA  
S_LOAD  
S_DATA  
S_CLOCK  
C11  
C16  
10u  
0.01u  
VEE  
ICS84320-01  
VCC  
R1  
125  
R3  
125  
Zo = 50 Ohm  
IN+  
C14  
0.1u  
TL1  
+
-
C15  
0.1u  
Zo = 50 Ohm  
IN-  
TL2  
R2  
84  
R4  
84  
FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT  
www.icst.com/products/hiperclocks.html  
84320AY-01  
REV. A AUGUST 24, 2004  
10  
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
• The differential 50output traces should have the  
same length.  
The following component footprints are used in this layout  
example:  
• Avoid sharp angles on the clock trace.Sharp angle  
turns cause the characteristic impedance to change on  
the transmission lines.  
All the resistors and capacitors are size 0603.  
POWER AND GROUNDING  
Place the decoupling capacitors C14 and C15, as close as pos-  
sible to the power pins. If space allows, placement of the  
decoupling capacitor on the component side is preferred. This  
can reduce unwanted inductance between the decoupling ca-  
pacitor and the power pin caused by the via.  
• Keep the clock traces on the same layer.Whenever pos-  
sible, avoid placing vias on the clock traces. Placement  
of vias on the traces can affect the trace characteristic  
impedance and hence degrade signal integrity.  
To prevent cross talk, avoid routing other signal traces in  
parallel with the clock traces. If running parallel traces is  
unavoidable, allow a separation of at least three trace  
widths between the differential clock trace and the other  
signal trace.  
Maximize the power and ground pad sizes and number of vias  
capacitors.This can reduce the inductance between the power  
and ground planes and the component power and ground pins.  
The RC filter consisting of R7, C11, and C16 should be placed  
as close to the VCCA pin as possible.  
• Make sure no other signal traces are routed between the  
clock trace pair.  
CLOCK TRACES AND TERMINATION  
• The matching termination resistors should be located as  
close to the receiver input pins as possible.  
Poor signal integrity can degrade the system performance or  
cause system failure. In synchronous high-speed digital systems,  
the clock signal is less tolerant to poor signal integrity than other  
signals. Any ringing on the rising or falling edge or excessive ring  
back can cause system failure. The shape of the trace and the  
trace delay might be restricted by the available space on the board  
and the component location.While routing the traces, the clock  
signal traces should be routed first and should be locked prior to  
routing other signal traces.  
CRYSTAL  
The crystal X1 should be located as close as possible to the pins  
25 (XTAL1) and 24 (XTAL2). The trace length between the X1  
and U1 should be kept to a minimum to avoid unwanted parasitic  
inductance and capacitance. Other signal traces should not be  
routed near the crystal traces.  
GND  
X1  
C1  
C2  
VCC  
VIA  
U1  
PIN 1  
C16  
C11  
VCCA  
R7  
Close to the input  
pins of the  
receiver  
R1  
R3  
R2  
R4  
C15  
TL1  
C14  
TL1N  
TL1, TL21N are 50 Ohm  
traces and equal length  
FIGURE 5B. PCB BOARD LAYOUT FOR ICS84320-01  
www.icst.com/products/hiperclocks.html  
84320AY-01  
REV. A AUGUST 24, 2004  
11  
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
POWER CONSIDERATIONS  
This section provides information on power dissipation and junction temperature for the ICS84320-01.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the ICS84320-01 is the sum of the core power plus the power dissipated in the load(s).  
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 155mA = 537.08mW  
Power (outputs)MAX = 30.2mW/Loaded Output pair  
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW  
Total Power_MAX (3.465V, with all outputs switching) = 537.08mW + 60.4mW = 597.5mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the  
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.  
The equation for Tj is as follows: Tj = θJA * Pd_total + TA  
Tj = JunctionTemperature  
θJA = Junction-to-AmbientThermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = AmbientTemperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a  
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W perTable 8 below.  
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:  
70°C + 0.598W * 42.1°C/W = 95.2°C. This is well below the limit of 125°C.  
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,  
and the type of board (single layer or multi-layer).  
TABLE 8. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION  
θJA byVelocity (Linear Feet per Minute)  
0
200  
55.9°C/W  
42.1°C/W  
500  
50.1°C/W  
39.4°C/W  
Single-Layer PCB, JEDEC Standard Test Boards  
Multi-Layer PCB, JEDEC Standard Test Boards  
67.8°C/W  
47.9°C/W  
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.  
84320AY-01  
www.icst.com/products/hiperclocks.html  
REV. A AUGUST 24, 2004  
12  
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
3. Calculations and Equations.  
The purpose of this section is to derive the power dissipated into the load.  
LVPECL output driver circuit and termination are shown in Figure 6.  
VCCO  
Q1  
VOUT  
R L  
50  
VCCO - 2V  
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION  
To calculate worst case power dissipation into the load, use the following equations which assume a 50load, and a termination  
voltage ofV - 2V.  
CCO  
For logic high, VOUT = V  
= V  
– 1.0V  
OH_MAX  
CCO_MAX  
)
= 1.0V  
OH_MAX  
(V  
- V  
CCO_MAX  
For logic low, V = V  
= V  
– 1.7V  
OUT  
OL_MAX  
CCO_MAX  
)
= 1.7V  
OL_MAX  
(V  
- V  
CCO_MAX  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
))  
Pd_H = [(V  
– (V  
- 2V))/R ] * (V  
- V  
) = [(2V - (V  
- V  
/R ] * (V  
- V ) =  
OH_MAX  
OH_MAX  
CCO_MAX  
CCO_MAX  
OH_MAX  
CCO_MAX  
OH_MAX  
CCO_MAX  
L
L
[(2V - 1V)/50) * 1V = 20.0mW  
))  
Pd_L = [(V  
– (V  
- 2V))/R ] * (V  
- V  
) = [(2V - (V  
- V  
/R ] * (V  
- V  
) =  
OL_MAX  
CCO_MAX  
CCO_MAX  
OL_MAX  
CCO_MAX  
OL_MAX  
CCO_MAX  
OL_MAX  
L
[(2V - 1.7V)/50) * 1.7V = 10.2mW L  
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW  
84320AY-01  
www.icst.com/products/hiperclocks.html  
REV. A AUGUST 24, 2004  
13  
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
RELIABILITY INFORMATION  
TABLE 9. θJAVS. AIR FLOW TABLE  
θJA byVelocity (Linear Feet per Minute)  
0
200  
55.9°C/W  
42.1°C/W  
500  
50.1°C/W  
39.4°C/W  
Single-Layer PCB, JEDEC Standard Test Boards  
Multi-Layer PCB, JEDEC Standard Test Boards  
67.8°C/W  
47.9°C/W  
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.  
TRANSISTOR COUNT  
The transistor count for ICS84320-01 is: 3776  
84320AY-01  
www.icst.com/products/hiperclocks.html  
REV. A AUGUST 24, 2004  
14  
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
PACKAGE OUTLINE -Y SUFFIX  
TABLE 10. PACKAGE DIMENSIONS  
JEDEC VARIATION  
ALL DIMENSIONS IN MILLIMETERS  
BBA  
SYMBOL  
MINIMUM  
NOMINAL  
MAXIMUM  
N
A
32  
--  
--  
--  
1.60  
0.15  
1.45  
0.45  
0.20  
A1  
A2  
b
0.05  
1.35  
0.30  
0.09  
1.40  
0.37  
c
--  
D
9.00 BASIC  
7.00 BASIC  
5.60 Ref.  
9.00 BASIC  
7.00 BASIC  
5.60 Ref.  
0.80 BASIC  
0.60  
D1  
D2  
E
E1  
E2  
e
L
0.45  
0.75  
θ
--  
0°  
7°  
ccc  
--  
--  
0.10  
Reference Document: JEDEC Publication 95, MS-026  
84320AY-01  
www.icst.com/products/hiperclocks.html  
REV. A AUGUST 24, 2004  
15  
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
TABLE 11. ORDERING INFORMATION  
Part/Order Number  
Marking  
Package  
Count  
Temperature  
0°C to 70°C  
0°C to 70°C  
0°C to 70°C  
ICS84320AY-01  
ICS84320AY-01T  
ICS84320AY-01LN  
ICS84320AY-01  
ICS84320AY-01  
ICS84320A01N  
32 Lead LQFP  
250 per tray  
1000  
32 Lead LQFP on Tape and Reel  
32 Lead "Lead-Free/Annealed" LQFP 250 per tray  
32 Lead "Lead-Free/Annealed" LQFP  
ICS84320AY-01LNT  
ICS84320A01N  
1000  
0°C to 70°C  
on Tape and Reel  
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use  
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use  
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are  
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS  
product for use in life support devices or critical medical instruments.  
84320AY-01  
www.icst.com/products/hiperclocks.html  
REV. A AUGUST 24, 2004  
16  
ICS84320-01  
Integrated  
Circuit  
Systems, Inc.  
780MH  
Z
, CRYSTAL  
-
TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY  
SYNTHESIZER  
REVISION HISTORY SHEET  
Description of Change  
Rev  
A
Table  
T11  
Page  
7
Date  
7/2/04  
8/24/04  
Updated Typical Phase Noise plots and format.  
A
16  
Ordering Information Table - added Lead Free Part/Order Number.  
84320AY-01  
www.icst.com/products/hiperclocks.html  
REV. A AUGUST 24, 2004  
17  

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