ICS843246AMT [ICSI]
FEMTOCLOCKS? CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER; FEMTOCLOCKS⑩ CRYSTAL - TO- 3.3V LVPECL频率合成W /综合扇出缓冲器
| 型号： | ICS843246AMT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER |
| 文件： | 总15页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS843246
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS843246 is a Crystal-to-3.3V LVPECL • Six LVPECL outputs
ICS
HiPerClockS™
Clock Synthesizer/Fanout Buffer designed for
• Crystal oscillator interface
Fibre Channel and Gigabit Ethernet appli-
cations and is a member of the HiperClockS™
family of High Performance Clock Solutions
• Output frequency range: 53.125MHz to 333.3333MHz
• Crystal input frequency range: 25MHz to 33.333MHz
from ICS. The output frequency can be set using the fre-
quency select pins and a 25MHz crystal for Ethernet
frequencies, or a 26.5625MHz crystal for a Fibre Channel.
The low phase noise characteristics of the ICS843246
make it an ideal clock for these demanding applications.
• RMS phase jitter at 125MHz, using a 25MHz crystal
(1.875MHz to 20MHz): 0.41ps (typical)
• Full 3.3V or 3.3V core, 2.5V output supply mode
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard and lead-free RoHS-compliant
packages
SELECT FUNCTION TABLE
Inputs
Function
FB_SEL N_SEL1 N_SEL0 M Divide N Divide
M/N
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
20
20
20
20
24
24
24
24
2
4
10
5
5
4
8
2.5
8
3
4
6
6
4
12
2
BLOCK DIAGRAM
PIN ASSIGNMENT
VCCO
VCCO
1
24 Q3
Q0
2
3
4
23
22
21
20
nQ3
Q4
nQ4
Q5
nQ2
Q2
nQ1
nQ0
Pullup
PLL_BYPASS
5
Q1
Q1
6
19 nQ5
nQ0
Q0
PLL_BYPASS
VCCA
7
8
9
10
11
12
N_SEL1
VEE
VEE
N_SEL0
XTAL_OUT
XTAL_IN
18
17
16
15
14
13
1
0
nQ1
Output
Divider
XTAL_IN
OSC
PLL
Q2
VCC
FB_SEL
XTAL_OUT
nQ2
ICS843246
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm
body package
Q3
Feedback
Divider
nQ3
M Package
TopView
Pulldown
Pullup
Q4
FB_SEL
N_SEL1
nQ4
24-LeadTSSOP
4.40mm x 7.8mm x 0.92mm
body package
Pullup
N_SEL0
Q5
G Package
TopView
nQ5
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843246AM
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REV.A SEPTEMBER 29, 2005
1
PRELIMINARY
ICS843246
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
VCCO
Type
Description
Power
Output
Output
Output
Output supply pins.
3, 4
nQ2, Q2
nQ1, Q1
nQ0, Q0
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
5, 6
7, 8
Differential output pair. LVPECL interface levels.
Selects between the PLL and crystal inputs as the input to the dividers.
9
PLL_BYPASS
Input
Pullup
When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT.
LVCMOS / LVTTL interface levels.
10
11
12
VCCA
VCC
Power
Power
Analog supply pin.
Core supply pin.
FB_SEL
Input Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels.
13,
14
15,
18
XTAL_IN,
XTAL_OUT
N_SEL0
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Input
Input
Pullup
Output frequency select pin. LVCMOS/LVTTL interface levels.
N_SEL1
16, 17
19, 20
21, 22
23, 24
VEE
Negative supply pin.
nQ5, Q5
nQ4, Q4
nQ3, Q3
Output
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
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REV.A SEPTEMBER 29, 2005
2
PRELIMINARY
ICS843246
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TABLE 3. CRYSTAL FUNCTION TABLE
Inputs
Function
XTAL (MHz) FB_SEL N_SEL1 N_SEL0
M
20
20
20
20
24
24
24
24
20
24
24
24
24
20
20
20
20
20
20
20
20
20
20
20
20
VCO (MHz)
500
N
2
Output (MHz)
250
25
25
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
500
4
125
25
500
5
100
25
500
8
62.5
25
600
3
200
25
600
4
150
25
600
6
100
25
600
12
5
50
26.5625
26.5625
26.5625
26.5625
26.5625
30
531.25
637.5
637.5
637.5
637.5
600
106.25
212.5
159.375
106.25
53.125
300
3
4
6
12
2
30
600
4
150
30
600
5
120
30
600
8
75
31.25
31.25
31.25
31.25
33.3333
33.3333
33.3333
33.3333
625
2
312.5
156.25
125
625
4
625
5
625
8
78.125
333.3333
166.6667
133.3333
83.3333
666.6667
666.6667
666.6667
666.6667
2
4
5
8
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REV.A SEPTEMBER 29, 2005
3
PRELIMINARY
ICS843246
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
CC
Inputs, V
-0.5V to VCC + 0.5V
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
24 Lead SOIC
24 LeadTSSOP
JA
50°C/W (0 lfpm)
70°C/W (0 mps)
StorageTemperature, T
-65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
3.135
3.3
V
107
7
mA
mA
ICCA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.465
3.465
2.625
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
2.375
2.5
V
107
7
mA
mA
ICCA
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
-0.3
FB_SEL
V
CC = VIN = 3.465V
CC = VIN = 3.465V
150
µA
IIH
Input High Current
PLL_BYPASS,
N_SEL0, N_SEL1
V
5
µA
µA
µA
FB_SEL
V
V
CC = 3.465V, VIN = 0V
CC = 3.465V, VIN = 0V
-5
IIL
Input Low Current
PLL_BYPASS,
N_SEL0, N_SEL1
-150
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REV.A SEPTEMBER 29, 2005
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PRELIMINARY
ICS843246
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
25
33.333
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pf parallel resonant crystal.
TABLE 6A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
53.125
333.33
MHz
125MHz, Integration Range:
1.875MHz - 20MHz
tjit(Ø)
RMS Phase Jitter (Random)
0.41
ps
tsk(o)
tR / tF
odc
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
TBD
380
50
ps
ps
ꢀ
20ꢀ to 80ꢀ
tLOCK
1
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
53.125
333.33
MHz
125MHz, Integration Range:
1.875MHz - 20MHz
tjit(Ø)
RMS Phase Jitter (Random)
0.41
ps
tsk(o)
tR / tF
odc
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
TBD
360
50
ps
ps
ꢀ
20ꢀ to 80ꢀ
tLOCK
1
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
843246AM
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REV.A SEPTEMBER 29, 2005
5
PRELIMINARY
ICS843246
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TYPICAL PHASE NOISE AT 125MHZ @ 3.3V
0
-10
-20
-30
-40
Gb Ethernet Filter
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.41ps (typical)
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
Raw Phase Noise Data
-160
-170
-180
-190
Phase Noise Result by adding
Gb Ethernet Filter to raw data
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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REV.A SEPTEMBER 29, 2005
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PRELIMINARY
ICS843246
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2.8V 0.04V
2V
2V
SCOPE
SCOPE
VCC
VCCA, VCCO
,
VCC
VCCA
,
Qx
Qx
VCCO
LVPECL
LVPECL
VEE
nQx
nQx
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQ0:nQ5
nQx
Qx
Q0:Q5
tPW
tPERIOD
nQy
tPW
Qy
odc =
x 100ꢀ
tsk(o)
tPERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80ꢀ
tF
80ꢀ
VSWING
20ꢀ
Clock
20ꢀ
Outputs
tR
OUTPUT RISE/FALL TIME
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PRELIMINARY
ICS843246
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843246 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA and
VCCO should be individually connected to the power supply
plane through vias, and bypass capacitors should be used
for each pin. To achieve optimum jitter performance, power
supply isolation is required. Figure 1 illustrates how a 10Ω
resistor along with a 10μF and a .01μF bypass capacitor
should be connected to each VCCA pin. The 10Ω resistor
can also be replaced by a ferrite bead.
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
below were determined using an 18pF parallel resonant
crystal and were chosen to minimize the ppm error.
The ICS843246 has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2
XTAL_OUT
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
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REV.A SEPTEMBER 29, 2005
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PRELIMINARY
ICS843246
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS CONTROL PINS:
LVPECL OUTPUT
All control pins have internal pull-ups or pull-downs; additional All unused LVPECL outputs can be left floating. We
resistance is not required but can be added for additional recommend that there is no trace attached. Both sides of the
protection. A 1kΩ resistor can be used.
differential output pair should either be left floating or
terminated.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
designed to drive 50Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 3A and
3B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate to
guarantee compatibility across all printed circuit and clock
component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, termi-
nating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUTTERMINATION
FIGURE 3B. LVPECL OUTPUTT ERMINATION
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PRELIMINARY
ICS843246
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for close to ground level. The R3 in Figure 4B can be eliminated
2.5V LVPECL driver. These terminations are equivalent to and the termination is shown in Figure 4C.
terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVERT ERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVERT ERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 4C. 2.5V LVPECLTERMINATION EXAMPLE
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REV.A SEPTEMBER 29, 2005
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PRELIMINARY
ICS843246
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843246.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843246 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 107mA = 370.75mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30mW = 180mW
Total Power_MAX (3.465V, with all outputs switching) = 370.75mW + 180mW = 550.75mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43°C/W perTable 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.551W * 43°C/W = 93.7°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 24-PIN SOIC, FORCED CONVECTION
θ
JA by Velocity (Linear Feet per Minute)
0
200
43°C/W
500
38°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
50°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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REV.A SEPTEMBER 29, 2005
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PRELIMINARY
ICS843246
Integrated
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Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT ANDTERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
CCO_MAX
OH_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V ) =
OH_MAX
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843246AM
www.icst.com/products/hiperclocks.html
REV.A SEPTEMBER 29, 2005
12
PRELIMINARY
ICS843246
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 8A. θJAVS. AIR FLOWTABLE FOR 24 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
43°C/W
500
38°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
50°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 8B. θJAVS. AIR FLOWTABLE FOR 24 LEADTSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS843246 is: 3863
843246AM
www.icst.com/products/hiperclocks.html
REV.A SEPTEMBER 29, 2005
13
PRELIMINARY
ICS843246
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX FOR 24 LEAD SOIC
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 9B. PACKAGE DIMENSIONS
TABLE 9A. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Millimeters
SYMBOL
Minimum
Maximum
Minimum
Maximum
N
A
24
N
A
24
--
2.65
--
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
B
0.10
2.05
0.33
0.18
15.20
7.40
A1
A2
b
0.05
0.80
0.19
0.09
7.70
2.55
0.51
0.32
15.85
7.60
C
D
E
c
D
E
6.40 BASIC
0.65 BASIC
e
1.27 BASIC
E1
e
4.30
4.50
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
0.45
0°
0.75
8°
L
α
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MS-013, MO-119
Reference Document: JEDEC Publication 95, MO-153
843246AM
www.icst.com/products/hiperclocks.html
REV.A SEPTEMBER 29, 2005
14
PRELIMINARY
ICS843246
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS843246AM
Marking
TBD
Package
Shipping Packaging Temperature
24 Lead SOIC
tube
1000 tape & reel
tube
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS843246AMT
ICS843246AMLF
ICS843246AMLFT
TBD
24 Lead SOIC
TBD
24 Lead "Lead-Free" SOIC
24 Lead "Lead-Free" SOIC
24 Lead TSSOP
TBD
1000 tape & reel
tube
ICS843246AG
ICS843246AGT
ICS843246AGLF
ICS843246AGLFT
ICS843246AG
ICS843246AG
TBD
24 Lead TSSOP
2500 tape & reel
tube
24 Lead "Lead-Free" TSSOP
24 Lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
843246AM
www.icst.com/products/hiperclocks.html
REV.A SEPTEMBER 29, 2005
15
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