ICS843252AGLF [ICSI]
FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER; FEMTOCLOCKS ™ CRYSTAL - TO- 3.3V LVPECL频率合成器
| 型号： | ICS843252AGLF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总17页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
FEATURES
GENERAL DESCRIPTION
• Fully integrated PLL
The ICS84314-02 is a general purpose quad
ICS
output frequency synthesizer and a member of
the HiPerClockS™family of High Performance
• Four differential 3.3V or 2.5V LVPECL outputs
HiPerClockS™
Clock Solutions from ICS.When the device uses • Selectable crystal oscillator interface
parallel loading, the M bits are programmable and
or LVCMOS/LVTTLTEST_CLK input
• Output frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
the output divider is hard-wired for divide by 2 thus providing
a frequency range of 125MHz to 350MHz. In serial program-
ming mode, the M bits are programmable and the output
divider can be set for either divide by 1, 2, 4 or divide by 8,
providing a frequency range of 31.25MHz to 700MHz.
Additionally, the device supports spread spectrum clocking
(SSC) for minimizing Electromagnetic Interference (EMI).The
low cycle-cycle jitter and broad frequency range of the
ICS84314-02 make it an ideal clock generator for a variety of
demanding applications which require high performance.
• Supports Spread Spectrum Clocking (SSC)
• Parallel interface for programming counter
and output dividers during power-up
• Serial 3 wire interface
• Cycle-to-cycle jitter: 20ps (typical)
• Output skew: TBD
• Output duty cycle: TBD
• Full 3.3V or mixed 3.3V core, 2.5V output operating supply
• 0°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-complaint
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
VCO_SEL
XTAL_SEL
M4
M5
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
TEST_CLK
XTAL_SEL
VCCA
TEST_CLK
0
ICS84314-02
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
M6
M7
S_LOAD
S_DATA
S_CLOCK
MR
XTAL_IN
1
OSC
M8
XTAL_OUT
VEE
÷ 16
VCC
VCCO
TopView
VCCO
Q0
nQ0
9
10 11 12 13 14 15 16
PLL
Output Divider N
÷1 Serial Mode
÷2 Parallel/Serial Mode
(Power-up Default)
÷4 Serial Mode
PHASE DETECTOR
Q1
nQ1
MR
0
1
VCO
Q2
nQ2
÷8 Serial Mode
Q3
nQ3
÷ M
÷2
S_LOAD
S_DATA
S_CLOCK
CONFIGURATION
INTERFACE
LOGIC
nP_LOAD
M0:M8
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84314AY-02
www.icst.com/products/hiperclocks.html
REV.B NOVEMBER 17, 2005
1
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes
operation using a 16MHz crystal. Valid PLL loop divider
values for different crystal or input frequencies are defined
in the Input Frequency Characteristics, Table 5, NOTE 1.
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 is passed directly to the M divider. On the LOW-to-HIGH tran-
sition of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or until
a serial event occurs. As a result, the M bits can be hardwired to
set the M divider to a specific default state that will automatically
occur during power-up. In parallel mode, the N output divider is
set to 2. In serial mode, the N output divider can be set for either
÷1, ÷2, ÷4 or ÷8. The relationship between the VCO frequency,
The ICS84314-02 features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A parallel-resonant, fundamental crystal is used
as the input to the on-chip oscillator.The output of the os-
cillator is divided by 16 prior to the phase detector.With a
16MHz crystal, this provides a 1MHz reference frequency.
The VCO of the PLL operates over a range of 250MHz to
700MHz.The output of the M divider is also applied to the
phase detector.
the crystal frequency and the M divider is defined as follows:
fxtal
16
x 2M
fVCO =
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table.Valid
M values for which the PLL will achieve lock for a 16MHz refer-
ence are defined as 125 ≤ M ≤ 350. The frequency out
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by ad-
justing the VCO control voltage. Note that for some values
of M (either too high or too low), the PLL will not achieve
lock. The output of the VCO is scaled by a divider prior to
being sent to each of the LVPECL output buffers.The divider
provides a 50% output duty cycle.
is defined as follows: fout =
fVCO x 1 = fxtal x 2M x 1
16
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW.The shift register is loaded by sampling the S_DATA bits
with the rising edge of S_CLOCK.The contents of the shift regis-
ter are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH.The M divide and N out-
put divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is
passed directly to the M divider and N output divider on each
rising edge of S_CLOCK.
The programmable features of the ICS84314-02 support
two input modes to program the M divider. The two input
operational modes are parallel and serial. Figure 1 shows
the timing diagram for each mode. In parallel mode, the
S
ERIAL
L
OADING
S_CLOCK
S_DATA
S_LOAD
*NULL *NULL SSC0 **N1 **N0 M8
M7
M6
M5
M4
M3 M2
M1
M0
t
t
H
S
nP_LOAD
t
S
P
ARALLEL LOADING
M0:M8
M, N
nP_LOAD
t
t
H
S
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
TABLE 1A. N OUTPUT DIVIDER FUNCTION TABLE (SERIAL LOAD)
TABLE 1B. SSC FUNCTION TABLE
N1 Logic Value N0 Logic Value
N Output Divide
SSC0
SSC State
Off (Power-up Default)
TBD
0
0
1
1
0
1
0
1
÷1
0
1
÷2 (Power-up Default)
÷4
÷8
*NOTE: The NULL timing slot must be observed.
**NOTE: “N” can only be controlled through serial loading.
84314AY-02
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REV.B NOVEMBER 17, 2005
2
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 2. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 5
29, 30, 31
M4, M5, M8,
M0, M1, M2
Input Pulldown
M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS / LVTTL interface levels.
3, 4, 32
6
M6, M7, M3
VEE
Input
Power
Power
Power
Output
Output
Output
Output
Pullup
Negative supply pin.
7
VCC
Core power supply pin.
8, 17
9, 10
11, 12
13, 14
15, 16
VCCO
Output supply pins.
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Differential output for the synthesizer. LVPECL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs Qx to go low and the inverted
18
MR
Input Pulldown outputs nQx to go high. When logic LOW, the internal dividers and
the outputs are enabled. Assertion of MR does not affect loaded
M values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS / LVTTL interface levels.
19
20
S_CLOCK
S_DATA
Input Pulldown
Input Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Selects between the crystal oscillator or test clock as the PLL
reference source. Selects XTAL inputs when HIGH. Selects
TEST_CLK when LOW. LVCMOS / LVTTL interface levels.
21
22
S_LOAD
VCCA
Input Pulldown
Power
Input
23
XTAL_SEL
TEST_CLK
Pullup
24
Input Pulldown Test clock input. LVCMOS / LVTTL interface levels.
XTAL_IN,
XTAL_OUT
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
25, 26
Input
Parallel load input. Determines when data present at M8:M0
is loaded into the M divider. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
27
28
nP_LOAD
VCO_SEL
Input Pulldown
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
84314AY-02
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REV.B NOVEMBER 17, 2005
3
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 4A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
X
S_LOAD
S_CLOCK
S_DATA
H
L
X
L
X
X
X
X
X
X
Reset. Forces outputs LOW.
Data
Data on M inputs passed directly to the M divider.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
L
L
L
↑
Data
X
L
L
↑
X
↑
L
X
H
H
Data
Data
X
L
L
L
H
H
H
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
TABLE 4B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
256
M8
0
128
M7
0
64
M6
1
32
M5
1
16
M4
1
8
M3
1
4
M2
1
2
M1
0
1
M0
1
VCO Frequency
(MHz)
M Divide
250
252
254
256
•
125
126
127
128
•
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
696
698
700
348
349
350
1
0
1
0
1
1
1
0
0
1
0
1
0
1
1
1
0
1
1
0
1
0
1
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input
frequency of 16MHz.
TABLE 4C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE (SERIAL PROGRAMMING MODE ONLY)
Input
Output Frequency (MHz)
Q0:Q3, nQ0:nQ3
N1 Logic
N0 Logic
N Divide
Minimum
250
Maximum
700
0
0
1
1
0
1
0
1
1
2
4
8
125
350
62.5
175
31.25
87.5
84314AY-02
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REV.B NOVEMBER 17, 2005
4
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5 V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
47.9°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
3.135
3.3
V
TBD
TBD
mA
mA
ICCA
TABLE 5B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.465
3.465
2.625
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
2.375
2.5
V
TBD
TBD
mA
mA
ICCA
84314AY-02
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REV.B NOVEMBER 17, 2005
5
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 5C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 85°C
Symbol
VIH
Parameter
Input High Voltage
Input Low Voltage
M0:M2, M4, M5, M8, MR,
Test Conditions
Minimum Typical Maximum Units
2
VCC + 0.3
0.8
V
V
VIL
-0.3
nP_LOAD, S_CLOCK,
S_DATA, S_LOAD
M3, M6, M7,
V
CC = VIN = 3.465V
150
µA
Input
High Current
IIH
VCC = VIN = 3.465V
VCC = VIN = 3.465V
5
µA
µA
XTAL_SEL, VCO_SEL
TEST_CLK
200
M0:M2, M4, M5, M8, MR,
nP_LOAD, S_CLOCK,
S_DATA, S_LOAD
VCC = 3.465V,
VIN = 0V
-5
µA
µA
Input
Low Current
IIL
VCC = 3.465V,
VIN = 0V
M3, M6, M7,
XTAL_SEL, VCO_SEL
-150
TABLE 5D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCCO - 1.4
VCCO - 2.0
0.6
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. See "Parameter Measurement Information" section,
"Output Load Test Circuit" diagrams.
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
TEST_CLK; NOTE 1
10
40
40
50
MHz
MHz
MHz
XTAL_IN, XTAL_OUT;
NOTE 1
fIN
Input Frequency
12
S_CLOCK
NOTE 1: For the input crystal and reference frequency range, the M value must be set for the VCO to operate within the
250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 167 ≤ M ≤ 466.
Using the maximum frequency of 40MHz, valid values of M are 50 ≤ M ≤ 140.
TABLE 7. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
12
40
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
84314AY-02
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REV.B NOVEMBER 17, 2005
6
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 8A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FMAX
Output Frequency Range
31.25
700
MHz
ps
tjit(cc)
tjit(per)
tsk(o)
tR / tF
Cycle-to-Cycle Jitter; NOTE 1, 3
Period Jitter, RMS; NOTE 1
Output Skew; NOTE 2, 3
Output Rise/Fall Time
20
TBD
TBD
460
ps
ps
20% to 80%
ps
M to nP_LOAD
5
5
ns
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M to nP_LOAD
ns
5
ns
5
ns
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
ns
5
ns
FM
SSC Modulation Frequency; NOTE 4
SSC Modulation Factor; NOTE 4
Spectral Reduction; NOTE 4
Output Duty Cycle
30
33.33
0.6
kHz
%
FMF
0.4
10
50
SSCred
odc
7
dB
%
tLOCK
PLL Lock Time
1
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using crystal inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Spread Spectrum clocking enabled.
TABLE 8B. AC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO = 2.5V 5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FMAX
Output Frequency Range
31.25
700
MHz
ps
tjit(cc)
tjit(per)
tsk(o)
tR / tF
Cycle-to-Cycle Jitter; NOTE 1, 3
Period Jitter, RMS; NOTE 1
Output Skew; NOTE 2, 3
Output Rise/Fall Time
20
TBD
TBD
460
ps
ps
20% to 80%
ps
M to nP_LOAD
5
5
ns
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M to nP_LOAD
ns
5
ns
5
ns
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
ns
5
ns
FM
SSC Modulation Frequency; NOTE 4
SSC Modulation Factor; NOTE 4
Spectral Reduction; NOTE 4
Output Duty Cycle
30
33.33
0.6
kHz
%
FMF
0.4
10
50
SSCred
odc
7
dB
%
tLOCK
PLL Lock Time
1
ms
See notes in Table 8A above.
84314AY-02
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REV.B NOVEMBER 17, 2005
7
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
2.8V 0.04V
2V
SCOPE
SCOPE
VCC
VCCA
,
VCC
VCCA, VCCO
,
Qx
Qx
VCCO
LVPECL
LVPECL
VEE
nQx
nQx
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx
Qx
nQx
Qx
➤
➤
tcycle n
tcycle n+1
➤
➤
nQy
Qy
tjit(cc) = tcycle n –tcycle n+1
tsk(o)
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
VOH
VREF
80%
tF
80%
VSWING
20%
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Clock
20%
Outputs
tR
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
PERIOD JITTER
nQ0:nQ3
OUTPUT RISE/FALL TIME
Q0:Q3
tPW
tPERIOD
tPW
odc =
x 100%
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
84314AY-02
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REV.B NOVEMBER 17, 2005
8
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84314-02 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 2. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVPECL OUTPUT
For applications not requiring the use of the crystal oscillator All unused LVPECL outputs can be left floating. We
input, both XTAL_IN and XTAL_OUT can be left floating. recommend that there is no trace attached. Both sides of the
Though not required, but for additional protection, a 1kΩ differential output pair should either be left floating or
resistor can be tied from XTAL_IN to ground.
terminated.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the TEST_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
84314AY-02
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REV.B NOVEMBER 17, 2005
9
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
CRYSTAL INPUT INTERFACE
The ICS84314-02 has been characterized with 18pF parallel lel resonant crystal and were chosen to minimize the ppm
resonant crystals. The capacitor values, C1 and C2, shown in error.The optimum C1 and C2 values can be slightly adjusted
Figure 3 below were determined using a 25MHz, 18pF paral- for different board layouts.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
Figure 3. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- drive 50Ω transmission lines. Matched impedance techniques
tion for LVPECL outputs.The two different layouts mentioned should be used to maximize operating frequency and minimize
are recommended only as guidelines.
signal distortion. Figures 4A and 4B show two different lay-
outs which are recommended only as guidelines. Other suit-
FOUT and nFOUT are low impedance follower outputs that able clock layouts may exist and it would be recommended
generate ECL/LVPECL compatible outputs.Therefore, terminat- that the board designers simulate to guarantee compatibility
ing resistors (DC current path to ground) or current sources across all printed circuit and clock component process varia-
must be used for functionality. These outputs are designed to tions.
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUTTERMINATION
FIGURE 4B. LVPECL OUTPUTT ERMINATION
84314AY-02
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REV.B NOVEMBER 17, 2005
10
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for close to ground level. The R3 in Figure 5A can be eliminated
2.5V LVPECL driver.These terminations are equivalent to ter- and the termination is shown in Figure 5C.
minating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V
VCCO=2.5V
2.5V
2.5V
VCCO=2.5V
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driver
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 5A. 2.5V LVPECL DRIVERTERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVERTERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 5C. 2.5V LVPECLTERMINATION EXAMPLE
84314AY-02
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REV.B NOVEMBER 17, 2005
11
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
LAYOUT GUIDELINE
The schematic of the ICS84314-02 layout example used in guideline. The layout in the actual system will depend on the
this layout guideline is shown in Figure 6A. The ICS84314-02 selected component types, the density of the components,
recommended PCB board layout for this example is shown the density of the traces, and the stack up of the P.C. board.
in Figure 6B. This layout example is used as a general
Logic Input Pin Examples
C1
X1
C2
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VCC
VCC
ICS84314_02
24
RU1
1K
RU2
Not Install
U1
VCC
VCCO
To Logic
Input
pins
To Logic
R7
10
Input
pins
1
M4
M5
M6
M7
T_CLK
2
3
4
5
6
7
8
23
22
21
20
19
18
17
XTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
VCCO
VCCA
C11
RD1
Not Install
RD2
1K
M8
VCC
C16
10u
VEE
VCC
VCCO
0.01u
VCCO
C3
0.1u
C5
0.1u
C4
0.1u
Zo = 50 Ohm
+
-
Zo = 50 Ohm
R2
50
R1
50
VCC=3.3V
VCCO=3.3V
C6 (Option)
R3
50
0.1u
Zo = 50 Ohm
Zo = 50 Ohm
+
-
R5
50
R4
50
C7 (Option)
0.1u
R6
50
FIGURE 6A. SCHEMATIC OF 3.3V/3.3V RECOMMENDED LAYOUT
84314AY-02
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REV.B NOVEMBER 17, 2005
12
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
• The traces with 50Ω transmission lines TL1 and TL2
at FOUT and nFOUT should have equal delay and
run adjacent to each other. Avoid sharp angles on the
clock trace. Sharp angle turns cause the characteris-
tic impedance to change on the transmission lines.
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as
possible to the power pins. If space allows, placing the
decoupling capacitor at the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin generated by the via.
• Keep the clock trace on the same layer.Whenever pos-
sible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
• To prevent cross talk, avoid routing other signal traces
in parallel with the clock traces. If running parallel traces
is unavoidable, allow more space between the clock
trace and the other signal trace.
Maximize the pad size of the power (ground) at the decoupling
capacitor.Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the
power (ground) plane and the component power (ground) pins.
• Make sure no other signal trace is routed between the
clock trace pair.
If VCCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the VCCA as possible.
The matching termination resistors R1, R2, R3 and R4
should be located as close to the receiver input pins as
possible. Other termination schemes can also be used but
are not shown in this example.
CLOCKT RACES ANDTERMINATION
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality. Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than other
signals. Any ringing on the rising or falling edge or excessive
ring back can cause system failure. The trace shape and the
trace delay might be restricted by the available space on the
board and the component location. While routing the traces, the
clock signal traces should be routed first and should be locked
prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the
pins 25 (XTAL_IN) and 26 (XTAL_OUT). The trace length be-
tween the X1 and U1 should be kept to a minimum to avoid
unwanted parasitic inductance and capacitance. Other sig-
nal traces should not be routed near the crystal traces.
FIGURE 6B. PCB BOARD LAYOUT FOR ICS84314-02
84314AY-02
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REV.B NOVEMBER 17, 2005
13
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation tech- The ICS84314-02 triangle modulation frequency deviation will
nique for EMI reduction. When spread-spectrum is enabled, not exceed 0.6% down-spread from the nominal clock fre-
a 30kHz triangle waveform is used with 0.5% down-spread quency (+0.0%/-0.5%). An example of the amount of down
(+0.0% / -0.5%) from the nominal 200MHz clock frequency. spread relative to the nominal clock frequency can be seen in
An example of a triangle frequency modulation profile is shown the frequency domain, as shown in Figure 7B. The ratio of
in Figure 7A below. The ramp profile can be expressed as: this width to the fundamental frequency is typically 0.4%,
and will not exceed 0.6%. The resulting spectral reduction
• Fnom = Nominal Clock Frequency in Spread OFF mode
will be greater than 7dB, as shown in Figure 7B. It is impor-
(200MHz with 16MHz IN)
tant to note the ICS84314-02 7dB minimum spectral reduc-
• Fm = Nominal Modulation Frequency (30kHz)
tion is the component-specific EMI reduction, and will not
• δ = Modulation Factor (0.5% down spread)
necessarily be the same as the system EMI reduction.
1
(1 - δ) fnom + 2 fm x δ x fnom x t when 0 < t <
,
2 fm
1
1
fm
(1 - δ) fnom - 2 fm x δ x fnom x t when
< t <
2 fm
Δ − 10 dBm
Fnom
B
A
➤
(1 - δ) Fnom
δ = 0.4%
➤
➤
0.5/fm
1/fm
FIGURE 6A. TRIANGLE FREQUENCY MODULATION
FIGURE 6B. 200MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN
(A) SPREAD-SPECTRUM OFF
(B) SPREAD-SPECTRUM ON
84314AY-02
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REV.B NOVEMBER 17, 2005
14
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 9. θJAVS. AIR FLOWT ABLE FOR 32 LEAD LQFP
θ
JA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84314-02 is: 5051
84314AY-02
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REV.B NOVEMBER 17, 2005
15
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
D
9.00 BASIC
7.00 BASIC
5.60
D1
D2
E
9.00 BASIC
7.00 BASIC
5.60
E1
E2
e
0.80 BASIC
0.60
L
0.45
0.75
θ
0°
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
84314AY-02
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REV.B NOVEMBER 17, 2005
16
PRELIMINARY
ICS84314-02
Integrated
Circuit
Systems, Inc.
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 11. ORDERING INFORMATION
Part/Order Number
ICS84314AY-02
Marking
Package
Shipping Packaging Temperature
ICS84314AY02
ICS84314AY02
ICS84314A02L
ICS84314A02L
32 Lead LQFP
tray
0°C to 85°C
0°C to 85°C
0°C to 85°C
0°C to 85°C
ICS84314AY-02T
ICS84314AY-02LF
ICS84314AY-02LFT
32 Lead LQFP
1000 tape & reel
tray
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQFP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
84314AY-02
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REV.B NOVEMBER 17, 2005
17
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