ICS844246AMLF [ICSI]

FEMTOCLOCKS? CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER; FEMTOCLOCKS ™ CRYSTAL - TO- LVDS频率合成W /综合扇出缓冲器
ICS844246AMLF
型号: ICS844246AMLF
厂家: INTEGRATED CIRCUIT SOLUTION INC    INTEGRATED CIRCUIT SOLUTION INC
描述:

FEMTOCLOCKS? CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
FEMTOCLOCKS ™ CRYSTAL - TO- LVDS频率合成W /综合扇出缓冲器

晶体 外围集成电路 光电二极管 时钟
文件: 总13页 (文件大小:186K)
中文:  中文翻译
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PRELIMINARY  
ICS844246  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ C RYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS844246 is a Crystal-to-LVDS Clock Six LVDS outputs  
ICS  
HiPerClockS™  
Synthesizer/Fanout Buffer designed for Fibre  
Crystal oscillator interface  
Channel and Gigabit Ethernet applications and  
is a member of the HiperClockS™ family of  
High Performance Clock Solutions from ICS.  
Output frequency range: 53.125MHz to 333.3333MHz  
Crystal input frequency range: 25MHz to 33.333MHz  
The output frequency can be set using the frequency  
select pins and a 25MHz crystal for Ethernet fre-  
quencies, or a 26.5625MHz crystal for a Fibre Channel.  
The low phase noise characteristics of the ICS844246  
make it an ideal clock for these demanding applications.  
RMS phase jitter at 125MHz, using a 25MHz crystal  
(1.875MHz to 20MHz): 0.39ps (typical)  
Full 3.3V or 3.3V core, 2.5V output supply mode  
0°C to 70°C ambient operating temperature  
Industrial temperature information available upon request  
Available in both standard and lead-free RoHS-compliant  
packages  
SELECT FUNCTION TABLE  
Inputs  
Function  
FB_SEL N_SEL1 N_SEL0 M Divide N Divide  
M/N  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
20  
20  
20  
20  
24  
24  
24  
24  
2
4
10  
5
5
4
8
2.5  
8
3
4
6
6
4
12  
2
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VDDO  
VDDO  
1
24  
23  
22  
21  
20  
19  
18  
Q3  
Q0  
2
nQ3  
3
nQ2  
Q4  
nQ0  
4
Q2  
nQ4  
Pullup  
PLL_BYPASS  
nQ1  
5
Q5  
Q1  
6
Q1  
nQ5  
7
8
9
10  
11  
12  
nQ0  
Q0  
PLL_BYPASS  
VDDA  
N_SEL1  
GND  
GND  
N_SEL0  
XTAL_OUT  
XTAL_IN  
1
0
nQ1  
17  
16  
15  
14  
13  
Output  
Divider  
XTAL_IN  
OSC  
PLL  
Q2  
VDD  
FB_SEL  
XTAL_OUT  
nQ2  
ICS843246  
24-Lead, 300-MIL SOIC  
7.5mm x 15.33mm x 2.3mm  
body package  
Q3  
Feedback  
Divider  
nQ3  
M Package  
TopView  
Pulldown  
FB_SEL  
Q4  
Pullup  
nQ4  
N_SEL1  
24-LeadTSSOP  
4.40mm x 7.8mm x 0.92mm  
body package  
Pullup  
N_SEL0  
Q5  
G Package  
TopView  
nQ5  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on  
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications  
without notice.  
844246AM  
www.icst.com/products/hiperclocks.html  
REV.A SEPTEMBER 29, 2005  
1
PRELIMINARY  
ICS844246  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ C RYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER  
TABLE 1. PIN DESCRIPTIONS  
Number  
1, 2  
Name  
VDDO  
Type  
Description  
Power  
Output  
Output  
Output  
Output supply pins.  
3, 4  
nQ2, Q2  
nQ1, Q1  
nQ0, Q0  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
5, 6  
7, 8  
Differential output pair. LVDS interface levels.  
Selects between the PLL and crystal inputs as the input to the dividers.  
9
PLL_BYPASS  
Input  
Pullup  
When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT.  
LVCMOS / LVTTL interface levels.  
10  
11  
12  
VDDA  
VDD  
Power  
Power  
Analog supply pin.  
Core supply pin.  
FB_SEL  
Input Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels.  
13,  
14  
15,  
18  
XTAL_IN,  
XTAL_OUT  
N_SEL0  
Crystal oscillator interface. XTAL_IN is the input.  
XTAL_OUT is the output.  
Input  
Input  
Pullup  
Output frequency select pin. LVCMOS/LVTTL interface levels.  
N_SEL1  
16, 17  
19, 20  
21, 22  
23, 24  
GND  
Power supply ground.  
nQ5, Q5  
nQ4, Q4  
nQ3, Q3  
Output  
Output  
Output  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
TABLE 2. PIN CHARACTERISTICS  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum Typical Maximum Units  
Input Capacitance  
Input Pullup Resistor  
4
pF  
kΩ  
kΩ  
RPULLUP  
51  
51  
RPULLDOWN Input Pulldown Resistor  
844246AM  
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REV.A SEPTEMBER 29, 2005  
2
PRELIMINARY  
ICS844246  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ C RYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER  
CRYSTAL FUNCTION TABLE  
Inputs  
Function  
XTAL (MHz) FB_SEL N_SEL1 N_SEL0  
M
20  
20  
20  
20  
24  
24  
24  
24  
20  
24  
24  
24  
24  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
VCO (MHz)  
500  
N
2
Output (MHz)  
250  
25  
25  
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
500  
4
125  
25  
500  
5
100  
25  
500  
8
62.5  
25  
600  
3
200  
25  
600  
4
150  
25  
600  
6
100  
25  
600  
12  
5
50  
26.5625  
26.5625  
26.5625  
26.5625  
26.5625  
30  
531.25  
637.5  
637.5  
637.5  
637.5  
600  
106.25  
212.5  
159.375  
106.25  
53.125  
300  
3
4
6
12  
2
30  
600  
4
150  
30  
600  
5
120  
30  
600  
8
75  
31.25  
31.25  
31.25  
31.25  
33.3333  
33.3333  
33.3333  
33.3333  
625  
2
312.5  
156.25  
125  
625  
4
625  
5
625  
8
78.125  
333.3333  
166.6667  
133.3333  
83.3333  
666.6667  
666.6667  
666.6667  
666.6667  
2
4
5
8
844246AM  
www.icst.com/products/hiperclocks.html  
REV.A SEPTEMBER 29, 2005  
3
PRELIMINARY  
ICS844246  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ C RYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER  
ABSOLUTE MAXIMUM RATINGS  
SupplyVoltage, V  
4.6V  
NOTE: Stresses beyond those listed under Absolute  
Maximum Ratings may cause permanent damage to the  
DD  
Inputs, V  
-0.5V to VDD + 0.5V  
I
device.These ratings are stress specifications only.Functional  
operation of product at these conditions or any conditions be-  
yond those listed in the DC Characteristics or AC Character-  
istics is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect product reliability.  
Outputs, IO  
Continuous Current  
Surge Current  
10mA  
15mA  
PackageThermal Impedance, θ  
24 Lead SOIC  
24 LeadTSSOP  
JA  
50°C/W (0 lfpm)  
70°C/W (0 mps)  
StorageTemperature, T  
-65°C to 150°C  
STG  
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C  
Symbol Parameter  
Test Conditions  
Minimum  
3.135  
Typical  
3.3  
Maximum Units  
VDD  
VDDA  
VDDO  
IDD  
Core Supply Voltage  
3.465  
3.465  
3.465  
V
V
Analog Supply Voltage  
Output Supply Voltage  
Power Supply Current  
Analog Supply Current  
Output Supply Current  
3.135  
3.3  
3.135  
3.3  
V
125  
7
mA  
mA  
mA  
IDDA  
IDDO  
127  
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C  
Symbol Parameter  
Test Conditions  
Minimum  
3.135  
Typical  
3.3  
Maximum Units  
VDD  
VDDA  
VDDO  
IDD  
Core Supply Voltage  
3.465  
3.465  
2.625  
V
V
Analog Supply Voltage  
Output Supply Voltage  
Power Supply Current  
Analog Supply Current  
Output Supply Current  
3.135  
3.3  
2.375  
2.5  
V
125  
7
mA  
mA  
mA  
IDDA  
IDDO  
115  
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = 0°C TO 70°C  
Symbol Parameter  
Test Conditions  
Minimum Typical Maximum Units  
VIH  
VIL  
Input High Voltage  
2
VDD + 0.3  
0.8  
V
V
Input Low Voltage  
-0.3  
FB_SEL  
VDD = VIN = 3.465V  
150  
µA  
IIH  
Input High Current  
PLL_BYPASS,  
N_SEL0, N_SEL1  
V
DD = VIN = 3.465V  
VDD = 3.465V, VIN = 0V  
DD = 3.465V, VIN = 0V  
5
µA  
µA  
µA  
FB_SEL  
-5  
IIL  
Input Low Current  
PLL_BYPASS,  
N_SEL0, N_SEL1  
V
-150  
844246AM  
www.icst.com/products/hiperclocks.html  
REV.A SEPTEMBER 29, 2005  
4
PRELIMINARY  
ICS844246  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ C RYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER  
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ TA = 0°C TO 70°C  
Symbol Parameter Test Conditions Minimum  
Typical  
387  
Maximum Units  
VOD  
Differential Output Voltage  
mV  
mV  
V
Δ VOD  
VOS  
VOD Magnitude Change  
Offset Voltage  
40  
1.29  
50  
Δ VOS  
VOS Magnitude Change  
mV  
NOTE: Please refer to Parameter Measurement Information for output information.  
TABLE 4E. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C  
Symbol  
VOD  
Parameter  
Test Conditions  
Minimum  
Typical  
379  
Maximum Units  
Differential Output Voltage  
VOD Magnitude Change  
Offset Voltage  
mV  
mV  
V
Δ VOD  
VOS  
40  
1.24  
50  
Δ VOS  
VOS Magnitude Change  
mV  
TABLE 5. CRYSTAL CHARACTERISTICS  
Parameter  
Test Conditions  
Minimum Typical Maximum Units  
Mode of Oscillation  
Frequency  
Fundamental  
25  
33.333  
MHz  
Ω
Equivalent Series Resistance (ESR)  
Shunt Capacitance  
Drive Level  
50  
7
pF  
1
mW  
NOTE: Characterized using an 18pf parallel resonant crystal.  
844246AM  
www.icst.com/products/hiperclocks.html  
REV.A SEPTEMBER 29, 2005  
5
PRELIMINARY  
ICS844246  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ C RYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER  
TABLE 6A. AC CHARACTERISTICS, VDD =VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C  
Symbol Parameter  
Test Conditions  
Minimum Typical Maximum Units  
FOUT  
Output Frequency  
53.125  
333.33  
MHz  
125MHz, Integration Range:  
1.875MHz - 20MHz  
tjit(Ø)  
RMS Phase Jitter (Random)  
0.39  
ps  
tsk(o)  
tR / tF  
odc  
Output Skew; NOTE 1, 2  
Output Rise/Fall Time  
Output Duty Cycle  
PLL Lock Time  
TBD  
355  
50  
ps  
ps  
20ꢀ to 80ꢀ  
tLOCK  
1
ms  
See Parameter Measurement Information section.  
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.  
Measured at the output differential crossing points.  
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.  
TABLE 6B. AC CHARACTERISTICS, VDD =VDDA = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C  
Symbol Parameter  
Test Conditions  
Minimum Typical Maximum Units  
FOUT  
Output Frequency  
53.125  
333.33  
MHz  
125MHz, Integration Range:  
1.875MHz - 20MHz  
tjit(Ø)  
RMS Phase Jitter (Random)  
0.38  
ps  
tsk(o)  
tR / tF  
odc  
Output Skew; NOTE 1, 2  
Output Rise/Fall Time  
Output Duty Cycle  
PLL Lock Time  
TBD  
380  
50  
ps  
ps  
20ꢀ to 80ꢀ  
tLOCK  
1
ms  
See Parameter Measurement Information section.  
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.  
Measured at the output differential crossing points.  
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.  
844246AM  
www.icst.com/products/hiperclocks.html  
REV.A SEPTEMBER 29, 2005  
6
PRELIMINARY  
ICS844246  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ C RYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER  
TYPICAL PHASE NOISE AT 125MHZ @ 3.3V  
0
-10  
-20  
-30  
-40  
Gb Ethernet Filter  
125MHz  
RMS Phase Jitter (Random)  
1.875MHz to 20MHz = 0.39ps (typical)  
-50  
-60  
-70  
-80  
-90  
-100  
-110  
-120  
-130  
-140  
Raw Phase Noise Data  
-150  
-160  
-170  
-180  
-190  
Phase Noise Result by adding  
Gb Ethernet Filter to raw data  
1k  
10k  
100k  
1M  
10M  
100M  
OFFSET FREQUENCY (HZ)  
844246AM  
www.icst.com/products/hiperclocks.html  
REV.A SEPTEMBER 29, 2005  
7
PRELIMINARY  
ICS844246  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ C RYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER  
PARAMETER MEASUREMENT INFORMATION  
3.3V  
2.5V  
SCOPE  
Qx  
SCOPE  
Qx  
+ +  
3.3V 5ꢀ  
POWER SUPPLY  
LVDS  
POWER  
SUPPLY  
Float GND  
LVDS  
+
Float GND  
-
nQx  
nQx  
3.3V OUTPUT LOAD AC TEST CIRCUIT  
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT  
nQ0:nQ5  
nQx  
Qx  
Q0:Q5  
tPW  
tPERIOD  
nQy  
tPW  
Qy  
odc =  
x 100ꢀ  
tsk(o)  
tPERIOD  
OUTPUT SKEW  
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD  
VDD  
out  
80ꢀ  
tF  
80ꢀ  
DC Input  
LVDS  
VSWING  
20ꢀ  
Clock  
20ꢀ  
Outputs  
out  
VOS/Δ VOS  
tR  
OFFSET VOLTAGE SETUP  
OUTPUT RISE/FALL TIME  
VDD  
out  
LVDS  
DC Input  
100  
V
OD/Δ VOD  
out  
DIFFERENTIAL OUTPUT VOLTAGE SETUP  
844246AM  
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REV.A SEPTEMBER 29, 2005  
7
PRELIMINARY  
ICS844246  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ C RYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER  
APPLICATION INFORMATION  
POWER SUPPLY FILTERING TECHNIQUES  
As in any high speed analog circuitry, the power supply pins  
are vulnerable to random noise. The ICS844246 provides  
separate power supplies to isolate any high switching  
noise from the outputs to the internal PLL. VDD, VDDA and  
VDDO should be individually connected to the power supply  
plane through vias, and bypass capacitors should be used  
for each pin. To achieve optimum jitter performance, power  
supply isolation is required. Figure 1 illustrates how a 10Ω  
resistor along with a 10μF and a .01μF bypass capacitor  
should be connected to each VDDA pin. The 10Ω resistor  
can also be replaced by a ferrite bead.  
3.3V  
VDD  
.01μF  
.01μF  
10Ω  
VDDA  
10μF  
FIGURE 1. POWER SUPPLY FILTERING  
CRYSTAL INPUT INTERFACE  
below were determined using an 18pF parallel resonant  
crystal and were chosen to minimize the ppm error.  
The ICS844246 has been characterized with 18pF parallel  
resonant crystals. The capacitor values shown in Figure 2  
XTAL_OUT  
XTAL_IN  
C1  
22p  
X1  
18pF Parallel Crystal  
C2  
22p  
Figure 2. CRYSTAL INPUt INTERFACE  
844246AM  
www.icst.com/products/hiperclocks.html  
REV.A SEPTEMBER 29, 2005  
8
PRELIMINARY  
ICS844246  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ C RYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER  
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS  
INPUTS:  
OUTPUTS:  
LVCMOS CONTROL PINS:  
LVDS  
All control pins have internal pull-ups or pull-downs; additional All unused LVDS output pairs can be either left floating or  
resistance is not required but can be added for additional terminated with 100Ω across. If they are left floating, we  
protection. A 1kΩ resistor can be used.  
recommend that there is no trace attached.  
3.3V, 2.5V LVDS DRIVER TERMINATION  
A general LVDS interface is shown in Figure 3. In a 100Ω require a matched load termination of 100Ω across near  
differential transmission line environment, LVDS drivers the receiver input.  
2.5V or 3.3V  
VDD  
LVDS_Driv er  
+
R1  
100  
-
100 Ohm Differential Transmission Line  
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION  
844246AM  
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REV.A SEPTEMBER 29, 2005  
9
PRELIMINARY  
ICS844246  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ C RYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER  
RELIABILITY INFORMATION  
TABLE 7A. θJAVS. AIR FLOW TABLE FOR 24 LEAD SOIC  
θJA byVelocity (Linear Feet per Minute)  
0
200  
43°C/W  
500  
38°C/W  
Multi-Layer PCB, JEDEC Standard Test Boards  
50°C/W  
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.  
TABLE 7B. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP  
θJA byVelocity (Meters per Second)  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
70°C/W  
65°C/W  
62°C/W  
TRANSISTOR COUNT  
The transistor count for ICS844246 is: 3887  
844246AM  
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REV.A SEPTEMBER 29, 2005  
10  
PRELIMINARY  
ICS844246  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ C RYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER  
PACKAGE OUTLINE - M SUFFIX FOR 24 LEAD SOIC  
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP  
TABLE 8B. PACKAGE DIMENSIONS  
TABLE 8A. PACKAGE DIMENSIONS  
Millimeters  
SYMBOL  
Millimeters  
SYMBOL  
Minimum  
Maximum  
Minimum  
Maximum  
N
A
24  
N
A
24  
--  
2.65  
--  
--  
1.20  
0.15  
1.05  
0.30  
0.20  
7.90  
A1  
A2  
B
0.10  
2.05  
0.33  
0.18  
15.20  
7.40  
A1  
A2  
b
0.05  
0.80  
0.19  
0.09  
7.70  
2.55  
0.51  
0.32  
15.85  
7.60  
C
D
E
c
D
E
6.40 BASIC  
0.65 BASIC  
e
1.27 BASIC  
E1  
e
4.30  
4.50  
H
h
10.00  
0.25  
0.40  
0°  
10.65  
0.75  
1.27  
8°  
L
0.45  
0°  
0.75  
8°  
L
α
α
aaa  
--  
0.10  
Reference Document: JEDEC Publication 95, MS-013, MO-119  
Reference Document: JEDEC Publication 95, MO-153  
844246AM  
www.icst.com/products/hiperclocks.html  
REV.A SEPTEMBER 29, 2005  
11  
PRELIMINARY  
ICS844246  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ C RYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER  
TABLE 9. ORDERING INFORMATION  
Part/Order Number  
ICS844246AM  
Marking  
Package  
Shipping Packaging Temperature  
TBD  
TBD  
24 Lead SOIC  
tube  
1000 tape & reel  
tube  
0°C to 70°C  
0°C to 70°C  
0°C to 70°C  
0°C to 70°C  
0°C to 70°C  
0°C to 70°C  
0°C to 70°C  
0°C to 70°C  
ICS844246AMT  
ICS844246AMLF  
ICS844246AMLFT  
ICS844246AG  
24 Lead SOIC  
TBD  
24 Lead "Lead-Free" SOIC  
24 Lead "Lead-Free" SOIC  
24 Lead TSSOP  
TBD  
1000 tape & reel  
tube  
ICS844246AG  
ICS844246AG  
TBD  
ICS844246AGT  
ICS844246AGLF  
ICS844246AGLFT  
24 Lead TSSOP  
2500 tape & reel  
tube  
24 Lead "Lead-Free" TSSOP  
24 Lead "Lead-Free" TSSOP  
TBD  
2500 tape & reel  
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use  
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use  
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are  
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS  
product for use in life support devices or critical medical instruments.  
844246AM  
www.icst.com/products/hiperclocks.html  
REV.A SEPTEMBER 29, 2005  
12  

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