ICS844252AG-04T [ICSI]
FEMTOCLOCKS? CRYSTAL-TO-LVDS CLOCK GENERATOR; FEMTOCLOCKS ™ CRYSTAL - TO- LVDS时钟发生器
| 型号： | ICS844252AG-04T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO-LVDS CLOCK GENERATOR |
| 文件： | 总12页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS844252-04
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
• Two differential LVDS outputs
The ICS844252-04 is a 10Gb/12Gb Ethernet
ICS
HiPerClockS™
Clock Generator and a member of the
HiPerClocksTM family of high performance
devices from ICS. The ICS844252-04 can
synthesize 10 Gigabit Ethernet and 12 Gigabit
• Crystal oscillator interface designed for
18pF parallel resonant crystals
• Crystal input frequency range: 19.33MHz - 30MHz
• Output frequency range: 145MHz - 187.5MHz
• VCO frequency range: 580MHz - 750MHz
Ethernet with a 25MHz crystal. It can also generate SATA
and 10Gb Fibre Channel reference clock frequencies with
the appropriate choice of crystals. The ICS844252-04 has
excellent phase jitter performance and is packaged in a
small 16-pin TSSOP, making it ideal for use in systems with
limited board space.
• RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):
0.36ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard and lead-free compliant
packages
CONFIGURATION TABLE WITH 25MHZ CRYSTAL
Inputs
Output Frequency
Application
Crystal Frequency Feedback VCO Frequency
(MHz)
N Output Divide
(MHz)
Divide
(MHz)
25
30
750
4
4
187.5
12 Gigabit Ethernet
10 Gigabit Ethernet
25
25
625
156.25
CONFIGURATION TABLE WITH SELECTABLE CRYSTALS
Inputs
Output Frequency
(MHz)
Application
Crystal Frequency Feedback VCO Frequency
N Output Divide
(MHz)
Divide
(MHz)
20
30
600
4
4
4
4
4
150
159.375
150
SATA
21.25
24
30
637.5
600
10 Gigabit Fibre Channel
SATA
25
25.5
30
25
637.5
750
159.375
187.5
10 Gigabit Fibre Channel
12 Gigabit Ethernet
25
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
OE
D
1
2
3
4
5
6
7
8
nQ1
Q1
16
15
14
13
12
11
10
9
XTAL_IN
XTAL_OUT
GND
Q
Pulldown
nPLL_SEL
LE
VDDO
OE
nPLL_SEL
VDDO
Q0
REF_CLK
CLK_SEL
VDD
VDDA
FREQ_SEL
Pulldown
REF_CLK
1
1
0
DIV. N
÷4
Q0
XTAL_IN
nQ0
VCO
nQ0
Phase
Detector
580MHz-750MHz
0
OSC
Q1
nQ1
ICS844252-04
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
XTAL_OUT
CLK_SEL
Pulldown
0 = ÷25 (default)
G Package
Top View
1 = ÷30
Pulldown
FREQ_SEL
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
844252AG-04
www.icst.com/products/hiperclocks.html
REV.A JANUARY 26, 2006
1
PRELIMINARY
ICS844252-04
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
nQ1, Q1
VDDO
Type
Description
Output
Power
Differential clock outputs. LVDS interface levels.
Output supply pins.
3, 6
Output enable. When HIGH, clock outputs follow clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS/LVTTL interface levels.
4
5
OE
Input
Input
Pullup
Selects between the PLL and reference clock as input to the divider.
nPLL_SEL
Pulldown When Low, selects PLL. When High, selects reference clock.
LVCMOS/LVTTL interface levels.
7, 8
9
Q0, nQ0
FREQ_SEL
VDDA
Output
Input
Differential clock outputs. LVDS interface levels.
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Analog supply pin.
10
Power
11
12
VDD
Power
Input
Core supply pin.
Clock select input. When Low, selects crystal inputs. When High,
Pulldown
CLK_SEL
selects REF_CLK. LVCMOS/LVTTL interface levels.
13
14
REF_CLK
GND
Input
Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
Power supply ground.
Power
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
15, 16
Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characterristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
kΩ
kΩ
RPULLUP
RPULLDOWN
51
51
844252AG-04
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REV.A JANUARY 26, 2006
2
PRELIMINARY
ICS844252-04
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA 89°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD =VDDA =VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.135
3.3
3.135
3.3
V
70
mA
mA
mA
IDDA
IDDO
11
40
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA =VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
REF_CLK,
CLK_SEL,
FREQ_SEL,
nPLL_SEL
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
IIH
Input High Current
OE
REF_CLK,
CLK_SEL,
FREQ_SEL,
nPLL_SEL
V
-5
IIL
Input Low Current
OE
VDD = 3.465V, VIN = 0V
-150
TABLE 3C. LVDS DC CHARACTERISTICS, VDD =VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum
Typical
400
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
40
1.25
50
Δ VOS
VOS Magnitude Change
mV
844252AG-04
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REV.A JANUARY 26, 2006
3
PRELIMINARY
ICS844252-04
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
19.33
30
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 5. AC CHARACTERISTICS, VDD =VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
145
187.5
MHz
ps
tsk(o)
Output Skew; NOTE 1, 2
TBD
0.36
156.25MHz @ Integration Range:
1.875MHz - 20MHz
159.375MHz @ Integration Range:
1.875MHz - 20MHz
187.5MHz @ Integration Range:
1.875MHz - 20MHz
ps
ps
ps
RMS Phase Jitter (Random);
NOTE 3
tjit(Ø)
0.38
0.38
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
375
50
ps
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plots following this section.
844252AG-04
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REV.A JANUARY 26, 2006
4
PRELIMINARY
ICS844252-04
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TYPICAL PHASE NOISE AT 156.25MHZ
0
-10
-20
-30
-40
Gb Ethernet Filter
156.25MHz
RMS Phase Noise Jitter
-50
-60
1.875MHz to 20MHz = 0.36ps (typical)
-70
-80
-90
-100
-110
-120
-130
-140
-150
Raw Phase Noise Data
-160
-170
-180
Phase Noise Result by adding a
Gb Ethernet Filter Filter to raw data
-190
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
844252AG-04
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REV.A JANUARY 26, 2006
5
PRELIMINARY
ICS844252-04
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
Phase Noise Plot
SCOPE
Qx
3.3V 5ꢀ
POWER SUPPLY
Phase Noise Mask
LVDS
+
Float GND
-
nQx
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD ACTEST CIRCUIT
RMS PHASE JITTER
nQx
Qx
nQ0, nQ1
Q0, Q1
tPW
tPERIOD
nQy
tPW
Qy
odc =
x 100ꢀ
tsk(o)
tPERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
➤
out
out
80ꢀ
tF
80ꢀ
VSWING
20ꢀ
LVDS
DC Input
100
V
OD/Δ VOD
Clock
20ꢀ
Outputs
➤
tR
OUTPUT RISE/FALLT IME
DIFFERENTIAL OUTPUTVOLTAGE SETUP
VDD
out
➤
DC Input
LVDS
out
VOS/Δ VOS
➤
OFFSETVOLTAGE SETUP
844252AG-04
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REV.A JANUARY 26, 2006
6
PRELIMINARY
ICS844252-04
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844252-04 pro-
vides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. VDD, VDDA,
and VDDO should be individually connected to the power
supply plane through vias, and bypass capacitors should
be used for each pin.To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844252-04 has been characterized with 18pF paral- parallel resonant crystal and were chosen to minimize the
lel resonant crystals.The capacitor values, C1 and C2, shown ppm error. The optimum C1 and C2 values can be slightly
in Figure 2 below were determined using a 25MHz, 18pF adjusted for different board layouts.
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
844252AG-04
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REV.A JANUARY 26, 2006
7
PRELIMINARY
ICS844252-04
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
OUTPUTS:
LVDS
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if
only partial outputs are used, it is recommended to termi-
nate the unused outputs.
3.3V
3.3V
LVDS
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVERT ERMINATION
844252AG-04
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REV.A JANUARY 26, 2006
8
PRELIMINARY
ICS844252-04
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844252-04.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844252-04 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 70mA = 242.6mW
Power (output)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 40mA = 138.6mW
Total Power_MAX = 242.6mW + 138.6mW = 381.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.
Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8°C/W per
Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.381W * 81.8°C/W = 101°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 16-LEADTSSOP, FORCED CONVECTION
θ
JA by Velocity (Linear Feet per Minute)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
844252AG-04
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REV.A JANUARY 26, 2006
9
PRELIMINARY
ICS844252-04
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOWT ABLE FOR 16 LEAD TSSOP
θ
JA by Velocity (Linear Feet per Minute)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS844252-04 is: 2234
844252AG-04
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REV.A JANUARY 26, 2006
10
PRELIMINARY
ICS844252-04
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 16 LEADTSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum Maximum
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
844252AG-04
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REV.A JANUARY 26, 2006
11
PRELIMINARY
ICS844252-04
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS844252AG-04
Marking
44251A04
44251A04
TBD
Package
Shipping Packaging
tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
16 Lead TSSOP
ICS844252AG-04T
ICS844252AG-04LF
ICS844252AG-04LFT
16 Lead TSSOP
2500 tape & reel
tube
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
844252AG-04
www.icst.com/products/hiperclocks.html
REV.A JANUARY 26, 2006
12
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