ICS8442AYIT [ICSI]
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER; 700MHZ ，晶体振荡器，差分LVDS频率合成器
| 型号： | ICS8442AYIT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER |
| 文件： | 总15页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS8442I is a general purpose, dual output • Dual differential LVDS outputs
ICS
Crystal-to-Differential LVDS High Frequency
• Selectable crystal oscillator interface or
LVCMOS/LVTTLTEST_CLK
HiPerClockS™
Synthesizer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8442I has a selectable TEST_CLK
• Output frequency range: 31.25MHz to 700MHz
• Crystal input frequency range: 10MHz to 25MHz
• VCO range: 250MHz to 700MHz
or crystal input. The TEST_CLK input accepts LVCMOS or
LVTTL input levels and translates them to LVDS levels. The
VCO operates at a frequency range of 250MHz to 700MHz.
The VCO frequency is programmed in steps equal to the value
of the input reference or crystal frequency.TheVCO and output
frequency can be programmed using the serial or parallel
interface to the configuration logic. The low phase noise
characteristics of the ICS8442I makes it an ideal clock source
for Gigabit Ethernet and Sonet applications.
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter: 3.5ps (typical)
• Cycle-to-cycle jitter: 18ps (typical)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
XTAL_SEL
TEST_CLK
0
32 31 30 29 28 27 26 25
XTAL_IN
1
M5
M6
M7
M8
N0
N1
nc
OSC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL_OUT
TEST_CLK
XTAL_SEL
VDDA
XTAL_OUT
ICS8442I
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
÷ 1
÷ 2
÷ 4
÷ 8
MR
0
1
GND
VCO
FOUT0
nFOUT0
FOUT1
nFOUT1
9
10 11 12 13 14 15 16
÷ M
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
M0:M8
N0:N1
Y Package
TopView
8442AYI
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REV. C MAY 10, 2005
1
ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
FUNCTIONAL DESCRIPTION
cific default state that will automatically occur during power-
up. The TEST output is LOW when operating in the parallel
input mode.The relationship between the VCO frequency, the
crystal frequency and the M divider is defined as follows:
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
fVCO = fxtal x M
The ICS8442I features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator.The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 250MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table.Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 10 ≤ M ≤ 28. The frequency
out is defined as follows:
FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-to-
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0.The internal registersT0 and T1 determine the state
of the TEST output as follows:
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock.The output of the
VCO is scaled by a divider prior to being sent to each of the
LVDS output buffers.The divider provides a 50% output duty cycle.
The programmable features of the ICS8442I support two in-
put modes to program the M divider and N output divider.The
two input operational modes are parallel and serial. Figure 1
shows the timing diagram for each mode. In parallel mode,
the nP_LOAD input is initially LOW. The data on inputs M0
through M8 and N0 and N1 is passed directly to the M divider
and N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a
serial event occurs. As a result, the M and N bits can be
hardwired to set the M divider and N output divider to a spe-
T1 T0
TEST Output
LOW
0
0
1
1
0
1
0
1
S_Data, Shift Register Input
Output of M divider
CMOS FOUT
S
ERIAL LOADING
S_CLOCK
T1
T0
*NULL N1
N0 M8
M7
M6
M5 M4
M3 M2
M1
M0
S_DATA
t
t
H
S
S_LOAD
nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N1
nP_LOAD
M, N
t
t
H
S
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
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REV. C MAY 10, 2005
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ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pullup
Description
1
M5
Input
Input
M divider inputs. Data latched on LOW-to-HIGH transistion
of nP_LOAD input. LVCMOS / LVTTL interface levels.
2, 3, 4,
28, 29,
30, 31, 32
M6, M7, M8,
M0, M1,
M2, M3, M4
Pulldown
Pulldown
Determines output divider value as defined in Table 3C
Function Table. LVCMOS / LVTTL interface levels.
5, 6
N0, N1
Input
7
nc
Unused
Power
No connect.
8, 16
GND
Power supply ground.
Test output which is ACTIVE in the serial mode of operation. Output
driven LOW in parallel mode. LVCMOS / LVTTL interface levels.
9
TEST
VDD
Output
Power
10, 13
11, 12
14, 15
Core supply pins.
FOUT1, nFOUT1 Output
FOUT0, nFOUT0 Output
Differential output for the synthesizer. LVDS interface levels.
Differential output for the synthesizer. LVDS interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inverted
17
MR
Input
Pulldown outputs nFOUTx to go high. When logic LOW, the internal dividers
and the outputs are enabled. Assertion of MR does not effect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS / LVTTL interface levels.
18
19
S_CLOCK
S_DATA
Input
Input
Pulldown
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
20
21
S_LOAD
VDDA
Input
Pulldown
Power
Analog supply pin.
Selects between crystal oscillator or test inputs as the PLL reference
22
XTAL_SEL
Input
Pullup
source. Selects XTAL inputs when HIGH. Selects TEST_CLK when
LOW. LVCMOS / LVTTL interface levels.
23
TEST_CLK
Input
Input
Pulldown Test clock input. LVCMOS / LVTTL interface levels.
XTAL_IN,
XTAL_OUT
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
24, 25
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
26
nP_LOAD
Input
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
27
VCO_SEL
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
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ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
Reset. When HIGH, forces the outputs to a differential
LOW state (FOUTx = LOW and nFOUTx = HIGH), but
does not effect loaded M, N, and T values.
H
L
X
L
X
X
X
X
X
X
X
X
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
Data Data
Data Data
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
L
L
L
↑
L
L
↑
X
↑
L
X
H
H
X
X
X
X
Data
Data
L
L
L
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
0
64
M6
0
32
M5
0
16
M4
0
8
M3
1
4
M2
0
2
M1
1
1
M0
0
VCO Frequency
(MHz)
M Divide
250
275
•
10
11
•
0
0
0
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
675
700
26
27
28
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
1
1
1
0
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency
of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Frequency (MHz)
N Divider Value
N1
N0
0
Minimum
250
Maximum
700
0
0
1
1
1
2
4
8
1
125
350
0
62.5
175
1
31.25
87.5
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REV. C MAY 10, 2005
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ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
3.465
3.465
155
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
V
mA
mA
IDDA
20
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
M0-M8, N0, N1, MR, nP_LOAD,
S_CLOCK, S_DATA, S_LOAD,
XTAL_SEL, VCO_SEL
2
VDD + 0.3
V
V
Input
VIH
High Voltage
TEST_CLK
2
V
DD + 0.3
0.8
M0-M8, N0, N1, MR, nP_LOAD,
S_CLOCK, S_DATA, S_LOAD,
XTAL_SEL, VCO_SEL
-0.3
-0.3
V
Input
VIL
Low Voltage
TEST_CLK
1.3
V
M0-M4, M6-M8, N0, N1, MR,
nP_LOAD, S_CLOCK, S_DATA,
S_LOAD,
VDD = VIN = 3.465V
150
5
µA
Input
IIH
High Current
M5, XTAL_SEL, VCO_SEL
VDD = VIN = 3.465V
M0-M4, M6-M8, N0, N1, MR,
nP_LOAD, S_CLOCK, S_DATA,
S_LOAD,
V
DD = 3.465V,
VIN = 0V
-5
µA
Input
IIL
Low Current
VDD = 3.465V,
VIN = 0V
M5, XTAL_SEL, VCO_SEL
-150
2.6
Output
VOH
TEST; NOTE 1
TEST; NOTE 1
V
V
High Voltage
Output
Low Voltage
VOL
0.5
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information section,
"3.3V Output Load Test Circuit".
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOD
Differential Output Voltage
250
450
600
50
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.125
1.4
1.6
50
Δ VOS
VOS Magnitude Change
mV
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REV. C MAY 10, 2005
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ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
TEST_CLK; NOTE 1
10
25
25
50
MHz
MHz
MHz
XTAL_IN, XTAL_OUT;
NOTE 1
fIN
Input Frequency
10
S_CLOCK
NOTE 1: For the input crystal and TEST_CLK frequency range the M value must be set for the VCO to operate within the
250MHz to 700MHz range. Using the minimum input frequency of 10MHz valid values of M are 25 ≤ M ≤ 70. Using the
maximum frequency of 25MHz valid values of M are 10 ≤ M ≤ 28.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
10
25
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 7. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
MHz
ps
FOUT
Output Frequency
31.25
700
32
N = 1, 2
N = 4
18
29
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 3
55
ps
tjit(per)
tsk(o)
tR / tF
Period Jitter, RMS; NOTE 1, 3
Output Skew; NOTE 2, 3
Output Rise/Fall Time
3.5
11
ps
15
ps
20% to 80%
150
750
ps
M, N to nP_LOAD
5
ns
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
ns
5
ns
5
ns
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
ns
5
47
ns
odc
tPW
Output Duty Cycle; NOTE 4
Output Pulse Width
PLL Lock Time
N > 1
N = 1
53
%
tPeriod/2 - 150
tPeriod/2 + 150
1
ps
tLOCK
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: In the Application Section, please refer to the application note, "Differential Duty Cycle Improvement".
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REV. C MAY 10, 2005
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ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
VDD
out
out
SCOPE
Qx
➤
DC Input
LVDS
Power Supply
Float GND
LVDS
+
-
nQx
VOS/Δ VOS
➤
OFFSET VOLTAGE SETUP
3.3V OUTPUT LOAD TEST CIRCUIT
VDD
nFOUTx
FOUTx
➤
out
LVDS
DC Input
100
V
OD/Δ VOD
nFOUTy
➤
FOUTy
out
tsk(o)
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OUTPUT SKEW
VOH
VREF
nFOUT0,
nFOUT1
FOUT0,
FOUT1
➤
➤
VOL
tcycle n
➤
tcycle n+1
➤
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
Cycle-to-Cycle Jitter
nFOUT0, nFOUT1
Period Jitter
80%
80%
FOUT0, FOUT1
VSWING
tPW
Clock
20%
20%
tPERIOD
Outputs
tF
tR
tPW
odc =
x 100%
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
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REV. C MAY 10, 2005
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ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
STORAGE AREA NETWORKS
A variety of technologies are used for interconnection of the quencies used as well as the settings for the ICS8442I to gen-
elements within a SAN.The tables below lists the common fre- erate the appropriate frequency.
Table 8. Common SANs Application Frequencies
Reference Frequency to SERDES
(MHz)
Crystal Frequency
(MHz)
Interconnect Technology
Gigabit Ethernet
Fibre Channel
Clock Rate
1.25 GHz
125, 250, 156.25
106.25, 53.125, 132.8125
125, 250
25, 19.53125
16.6015625, 25
25
FC1 1.0625 GHz
FC2 2.1250 GHz
Infiniband
2.5 GHz
Table 9. Configuration Details for SANs Applications
ICS8442I
ICS8442I
Interconnect
Technology
Crystal Frequency
(MHz)
Output Frequency
to SERDES
(MHz)
M & N Settings
M8 M7 M6 M5 M4 M3 M2 M1 M0 N1 N0
25
125
250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
1
0
1
1
0
1
1
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
1
0
1
1
1
1
1
1
0
0
1
0
0
1
0
0
0
1
25
Gigabit Ethernet
25
156.25
156.25
53.125
106.25
132.8125
125
19.53125
25
Fiber Channel 1
Fiber Channel 2
Infiniband
25
16.6015625
25
25
250
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS8442I provides sepa-
rate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VDD and VDDA, should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, better power supply
isolation is required. Figure 2 illustrates how a 10Ω along
|with a 10μF and a .01μF bypass capacitor should be
connected to each VDDA pin.
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 2. POWER SUPPLY FILTERING
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REV. C MAY 10, 2005
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ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel mode suitable for most applications. Additional accuracy can be
operation. The ICS8442I has a built-in crystal oscillator circuit. achieved by adding two small capacitors C1 and C2 as shown in
This interface can accept either a series or parallel crystal without Figure 3.Typical results using parallel 18pF crystals are shown
additional components and generate frequencies with accuracy inTable 10.
XTAL_IN
C1
18p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
Figure 3. CRYSTAL INPUt INTERFACE
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω differ- put. For a multiple LVDS outputs buffer, if only partial outputs
ential transmission line environment, LVDS drivers require a are used, it is recommended to terminate the un-used outputs.
matched load termination of 100Ω across near the receiver in-
3.3V
Zo = 50 Ohm
3.3V
LVDS_DRIVER
CLK
R1
100
nCLK
HiPerClockS
Zo = 50 Ohm
100Ω Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
DIFFERENTIAL DUTY CYCLE IMPROVEMENT
The schematic below is recommended for applications using the
÷1 output configuration for improving the differential duty cycle.
Vcc = 3.3V
R2
1.3k
R4
1.3k
C1
Zo = 50
+
-
R1
100
.1uf
C2
Zo = 50
.1uf
R3
800
R5
800
LVDS Driver
Receiver_dif
FIGURE 5. DIFFERENTIAL DUTY CYCLE IMPROVEMENT
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8442AYI
REV. C MAY 10, 2005
9
ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
LAYOUT GUIDELINE
The schematic of the ICS8442I layout example used in this lay-
out guideline is shown in Figure 5A. The ICS8442I recommended
PCB board layout for this example is shown in Figure 5B. This
layout example is used as a general guideline.The layout in the
actual system will depend on the selected component types, the
density of the components, the density of the traces, and the
stack up of the P.C. board.
C1
C2
X1
U1
VDD
1
2
3
4
5
6
7
8
24
R7
10
M5
M6
M7
M8
N0
N1
nc
X_OU T
T_CLK
nXTAL_SEL
VDDA
S_LOAD
S_DATA
S_CLOCK
MR
23
22
21
20
19
18
17
VDDA
C11
C16
0.01u
10u
GND
ICS8442
Zo = 50 Ohm
C14
0.1u
+
-
R1
100
C15
0.1u
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
R2
100
FIGURE 5A. RECOMMENDED SCHEMATIC LAYOUT
8442AYI
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REV. C MAY 10, 2005
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ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
traces should be routed first and should be locked prior to routing
other signal traces.
• The traces with 50Ω transmission linesTL1 and TL2 at
FOUT and nFOUT should have equal delay and run ad-
POWER AND GROUNDING
jacent to each other.Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
Maximize the pad size of the power (ground) at the decoupling
capacitor.Maximize the number of vias between power (ground)
and the pads.This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
If VCCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to theVCCA as possible.
• Make sure no other signal trace is routed between the
clock trace pair.
CLOCK TRACES AND TERMINATION
The matching termination resistors R1 and R2 should be located
as close to the receiver input pins as possible. Other termination
scheme can also be used but is not shown in this example.
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality. Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The trace shape and the trace
delay might be restricted by the available space on the board and
the component location.While routing the traces, the clock signal
CRYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL_OUT) and 25 (XTAL_IN).The trace length between the
X1 and U1 should be kept to a minimum to avoid unwanted para-
sitic inductance and capacitance. Other signal traces should not
be routed near the crystal traces.
GND
C1
C2
VDD
X1
VIA
U1
PIN 1
C16
C11
VDDA
R7
Close to the input
pins of the
receiver
For FOUT0/n FOUT0
output TL1, TL1N are
50 Ohm traces and
equal length
C14
TL1
R1
Same requirement fo
FOUT1/nFOUT1
C15
TL1N
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8442I
8442AYI
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REV. C MAY 10, 2005
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ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 10. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8442I is: 3662
8442AYI
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REV. C MAY 10, 2005
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ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 11. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
8442AYI
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REV. C MAY 10, 2005
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ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 12. ORDERING INFORMATION
Part/Order Number
ICS8442AYI
Marking
Package
Shipping Packaging
tray
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS8442AYI
ICS8442AYI
TBD
32 Lead LQFP
ICS8442AYIT
32 Lead LQFP
1000 tape & reel
tray
ICS8442AYILF
ICS8442AYILFT
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQFP
TBD
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
8442AYI
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REV. C MAY 10, 2005
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ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
T5
6
Input Frequency Characteristics Table - corrected minimum values from 14MHz to
10MHz and corrected within the note.
B
9/17/04
T6
T7
6
6
9
1
Crystal Characteristics - corrected minimum frequency from 14MHz to 10MHz.
AC Characteristics Table - added Note 4.
Added Application Note, "Differential Duty Cycle Improvement".
Changed XTAL1/2 naming convention to XTAL_IN/_OUT throughout the
datasheet.
B
12/16/04
Pin Assignment, corrected pin 24 to read XTAL_OUT from XTAL1 and pin 25 to
XTAL_IN from XTAL2.
2
6
6
Updated Figure 1, Parallel & Serial Load Operations diagram.
Crystal Characteristics Table - added Drive Level
AC Characteristics Table - changed test conditions for Cycle-to-Cycle Jitter from
ƒ ≥ = 350MHz to N = 1, 2 and ƒ< 350MHz to N = 4.
Corrected Crystal Input Interface diagram.
C
T6
T7
5/10/05
9
10
14
Updated Schematic Layout diagram.
Add Lead-Free note to Ordering Information Table.
T12
8442AYI
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REV. C MAY 10, 2005
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