ICS853014 [ICSI]
LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER; 低偏移， 1到5 2.5V / 3.3V的差分至LVPECL / ECL扇出缓冲器
| 型号： | ICS853014 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER |
| 文件： | 总17页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS853014 is a low skew, high performance • 5 differential LVPECL/ECL outputs
ICS
1-to-5, 2.5V/3.3V Differential-to-LVPECL/ECL
• 2 selectable differential LVPECL clock inputs
HiPerClockS™
Fanout Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. The ICS853014 has two selectable
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
clock inputs.
• Maximum output frequency: > 2GHz
• Output skew: 13ps (typical)
Guaranteed output and part-to-part skew characteristics
make the ICS853014 ideal for those applications
demanding well defined performance and repeatability.
• Part-to-part skew: 60ps (typical)
• Propagation delay: 460ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
VCC
nEN
VCC
nPCLK1
PCLK1
VBB
nPCLK0
PCLK0
CLK_SEL
VEE
D
nEN
Q
LE
PCLK0
nPCLK0
PCLK1
0
Q0
nQ0
1
nPCLK1
Q1
nQ1
9
10
CLK_SEL
nQ4
Q2
nQ2
ICS853014
20-LeadTSSOP
Q3
nQ3
VBB
6.5mm x 4.4mm x 0.92mm package body
G Package
Q4
nQ4
TopView
853014BG
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REV. C MAY 13, 2005
1
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
VEE
Type
Description
Output
Output
Output
Output
Output
Power
Differential output pair. LVPECL / ECL interface levels.
Differential output pair. LVPECL / ECL interface levels.
Differential output pair. LVPECL / ECL interface levels.
Differential output pair. LVPECL / ECL interface levels.
Differential output pair. LVPECL / ECL interface levels.
Negative supply pin.
3, 4
5, 6
7, 8
9, 10
11
Clock select input. When HIGH, selects CLK1, nCLK1 inputs.
Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVTTL / LVCMOS interface levels.
12
CLK_SEL
Input
13
14
PCLK0
nPCLK0
VBB
Input
Input
Pulldown Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Bias voltage.
15
Output
Input
16
PCLK1
nPCLK1
VCC
Pulldown Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Positive supply pins.
17
Input
18, 20
Power
Synchronizing clock enable. When LOW, clock outputs follow clock input.
Pulldown When HIGH, Q outputs are forced low, nQ outputs are forced high.
LVTTL / LVCMOS interface levels.
19
nEN
Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
RPULLDOWN
RVCC/2
Parameter
Test Conditions
Minimum
Typical
75
Maximum
Units
kΩ
Input Pulldown Resistor
Pullup/Pulldown Resistors
50
kΩ
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REV. C MAY 13, 2005
2
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
nEN
CLK_SEL
Selected Source
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK0, nPCLK0
PCLK1, nPCLK1
Q0:Q4
Disabled; LOW
Disabled; LOW
Enabled
nQ0:nQ4
Disabled; HIGH
Disabled; HIGH
Enabled
1
1
0
0
0
1
0
1
Enabled
Enabled
After nEN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the PCLK0, nPCLK0 and PCLK1, nPCLK1 inputs as
described in Table 3B.
Enabled
Disabled
nPCLK0, nPCLK1
PCLK0, PCLK1
nEN
nQ0:nQ4
Q0:Q4
FIGURE 1. nEN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Q0:Q4
Input to Output Mode
Polarity
PCLK0 or PCLK1 nPCLK0 or nPCLK1
nQ0:nQ4
HIGH
LOW
0
1
LOW
HIGH
LOW
HIGH
HIGH
LOW
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
853014BG
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ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
4.6V (LVPECL mode, VEE = 0)
-4.6V (ECL mode,VCC = 0)
-0.5V to VCC + 0.5V
Negative SupplyVoltage,VEE
Inputs,VI (LVPECL mode)
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
VBB Sing/Source, IBB
0.5mA
OperatingTemperature Range, TA -40°C to +85°C
Storage Temperature, TSTG -65°C to 150°C
PackageThermal Impedance, θJA 73.2°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
3.3
3.8
75
V
mA
TABLE 4B. DC CHARACTERISTICS, VCC = 3.3V, VEE = 0V
-40°C
Typ
25°C
85°C
Typ
Symbol Parameter
Min
Units
Max
Min
Typ
Max
Min
Max
2.175 2.275 2.38 2.225 2.295 2.375 2.22 2.295 2.365
1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63
V
V
V
V
V
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference; NOTE 2
2.075
1.43
1.86
2.36 2.075
1.765 1.43
2.36 2.075
1.765 1.43
2.36
1.765
1.98
1.98
3.3
1.86
1.2
1.98
3.3
1.86
1.2
VBB
Input High Voltage
Common Mode Range; NOTE 3, 4
1.2
3.3
V
VCMR
IIH
Input
D0, D1, D2, D3
150
150
150
µA
High Current nD0, nD1,n D2, nD3
-10
-10
-10
µA
µA
D0, D1, D2, D3
Input
Low Current
IIL
-150
-150
-150
nD0, nD1,n D2, nD3
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPLCK0 and PCLK1, nPCLK1
is VCC + 0.3V.
853014BG
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REV. C MAY 13, 2005
4
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
-40°C
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
1.58
0.88
1.56
0.965
Min
Max
Min
Max
1.375 1.475
0.605 0.745
1.275
1.425 1.495 1.57
0.625 0.72 0.815 0.64 0.735 0.83
1.42 1.495 1.565
V
V
V
V
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
1.275
0.63
1.56
1.275
-0.83
0.965
0.63
0.965 0.63
Input High Voltage
Common Mode Range; NOTE 2, 3
1.2
2.5
1.2
2.5
1.2
2.5
V
VCMR
IIH
Input
PCLK0, PCLK1
150
150
150
µA
High Current nPCLK0, nPCLK1
-10
-10
-10
µA
µA
PCLK0, PCLK1
Input
Low Current
IIL
-150
-150
-150
nPCLK0, nPCLK1
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
-40°C
Typ Max
25°C
85°C
Typ Max
Symbol Parameter
Units
Min
-1.125
-1.895
-1.225
-1.87
Min
-1.075
-1.875
-1.225
-1.87
Typ Max
Min
-1.08
-1.86
-1.225
-1.87
-1.025
-1.755
-0.92
-1.62
-0.94
-1.535
-1.005
-1.78
-0.93
-1.685
-0.94
-1.005
-1.765
-0.935
-1.67
V
V
V
V
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
-0.94
-1.535
-1.535
Output Voltage Reference;
NOTE 2
-1.44
-1.32
-1.44
-1.32
-1.44
-1.32
V
VBB
Input High Voltage
Common Mode Range;
NOTE 3, 4
VEE+1.2V
0
VEE+1.2V
0
VEE+1.2V
0
V
VCMR
Input
PCLK0, PCLK1
150
150
150
µA
IIH
IIL
High Current nPCLK0, nPCLK1
-10
-10
-10
µA
µA
PCLK0, PCLK1
Input
Low Current
-150
-150
-150
nPCLK0, nPCLK1
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
853014BG
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REV. C MAY 13, 2005
5
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 5. AC CHARACTERISTICS, VCC = 2.375V TO 3.8V, TA = -40°C TO 85°C
-40°C
25°C
85°C
Max Min Typ Max
>2
Symbol Parameter
Units
Min Typ
>2
Max Min Typ
fMAX
Output Frequency
>2
GHz
ps
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
355 440
13
525
25
376
460
13
550 400 500
595
25
tsk(o)
tsk(pp)
VPP
25
12
ps
Part-to-Part Skew; NOTE 3, 5
Peak-to-Peak Input Voltage; NOTE 4
105
105
130
ps
150 800 1800 150 800 1800 150 800 1800
mV
ps
tR/tF
Output Rise/Fall Time
Clock Enable Setup Time
Clock Enable Hold Time
20% to 80%
90
150
50
210
90
150
50
210
90
150
50
210
tS
tH
100
100
200
100
200
ps
ps
200 140
140
140
All parameters tested ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: The VCMR and VPP levels should be such that input low voltage never goes below VEE.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
853014BG
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REV. C MAY 13, 2005
6
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nPCLK0,
nPCLK1
VPP
LVPECL
VCMR
Cross Points
PCLK0,
PCLK1
nQx
VEE
VEE
-0.375V to -1.8V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
nQx
Qx
PART 1
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nPCLK0,
nPCLK1
80%
tF
80%
PCLK0,
PCLK1
VSWING
20%
Clock
20%
nQ0:nQ4
Outputs
tR
Q0:Q4
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nPCLK0,
nPCLK1
PCLK0,
PCLK1
tHOLD
nEN
tSET-UP
SETUP AND HOLD TIME
853014BG
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REV. C MAY 13, 2005
7
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows an example of the differential input that can be
wired to accept single ended levels. The reference voltage level
VBB generated from the device is connected to the negative input.
The C1 capacitor should be located as close as possible to the
input pin.
VDD(or VCC)
CLK_IN
+
VBB
-
C1
0.1uF
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV. C MAY 13, 2005
8
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V
ground level. The R3 in Figure 4B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 4C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
853014BG
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REV. C MAY 13, 2005
9
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
LVPECL CLOCK INPUT INTERFACE
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other gested here are examples only. If the driver is from another
differential signals. Both VSWING and VOH must meet the VPP and vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
VCMR input requirements. Figures 5A to 5E show interface
examples for the HiPerClockS PCLKx/nPCLKx input driven
by the most common driver types. The input interfaces sug-
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
nPCLK
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
FIGURE 5A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 5B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
R3
1K
R4
1K
Zo = 50 Ohm
Zo = 50 Ohm
C1
C2
LVDS
PCLK
PCLK
R5
100
nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 5C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 5E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
853014BG
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REV. C MAY 13, 2005
10
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
SCHEMATIC EXAMPLE
This application note provides general design guide using
ICS853014 LVPECL buffer.Figure 6shows a schematic example
of the ICS853014 LVPECL clock buffer.In this example, the in-
put is driven by an LVPECL driver.CLK_SEL is set at logic high
to select PCLK1/nPCLK1 input.
Zo = 50
+
Zo = 50
-
R2
50
R1
50
U1
3.3V
R12 1K
11
12
13
14
15
16
17
18
19
20
10
9
8
7
6
5
4
3
2
R3
50
VEE
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
3.3V
C3
0.1u
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VCC
Zo = 50
Zo = 50
3.3V
Zo = 50
Zo = 50
C2
nEN
VCC
nQ0
Q0
+
3.3V
1
0.1u
LVPECL Driv er
R9
50
R10
50
C1
0.1u ICS853014
-
R5
50
R4
50
C5
0.1u
R11
1K
R7
50
R6
50
C4
0.1u
FIGURE 6. EXAMPLE ICS853014 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC
853014BG
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REV. C MAY 13, 2005
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ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853014.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853014 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 75mA = 285mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30.94mW = 154.7mW
Total Power_MAX (3.8V, with all outputs switching) = 285mW + 154.7mW = 439.7mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θ
JA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.440W * 66.6°C/W = 114.3°C. This is well below the limit of 125°C
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
853014BG
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REV. C MAY 13, 2005
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ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.935V
CC_MAX
OH_MAX
)
= 0.935V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.67V
OL_MAX
CC_MAX
)
= 1.67V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
853014BG
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REV. C MAY 13, 2005
13
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θ byVelocity (Linear Feet per Minute)
JA
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853014 is: 373
Pin compatible with MC100LVEP14 and SY100EP14U
853014BG
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REV. C MAY 13, 2005
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ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
853014BG
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REV. C MAY 13, 2005
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ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS853014BG
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS853014BG
ICS853014BG
ICS853014BGL
ICS853014BGL
20 lead TSSOP
ICS853014BGT
ICS853014BGLF
ICS853014BGLFT
20 lead TSSOP
2500 tape & reel
tube
20 lead "Lead-Free" TSSOP
20 lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and
may be registered in certain jurisdictions.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853014BG
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REV. C MAY 13, 2005
16
ICS853014
LOW SKEW, 1-TO-5
2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
T4B
T4C
T4D
pg. 4
• 3.3V LVPECL table - VOH values changed @ 85° to 2.22V min. and
2.295V typical from 2.295V min. and 2.33V typical.
pg. 5
pg. 5
• 3.3V LVPECL table - VOH values changed @ 85° to 2.22V min. and
2.295V typical from 2.295V min. and 2.33V typical.
B
9/10/03
• 3.3V LVPECL table - VOH values changed @ 85° to 2.22V min. and
2.295V typical from 2.295V min. and 2.33V typical.
pg. 8
pg. 10
• Revised LVPECL Output Termination drawings.
• Revised Figure 5D.
T4B - T4D
T9
• LVPECL & ECL tables - deleted VPP row.
pgs. 4-5
C
C
3/18/04
5/13/05
• AC Table - added VPP row and changed max. value from 1200mV to 1800mV.
pg. 6
1
16
Features Section - added Lead-Free bullet.
Ordering Information Table - added Lead-Free part number.
853014BG
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REV. C MAY 13, 2005
17
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