ICS853016 [ICSI]
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER; 低偏移， 1到2差分至3.3V ， 5V LVPECL / ECL扇出缓冲器
| 型号： | ICS853016 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER |
| 文件： | 总13页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS853016
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
D
IFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT
B
UFFER
GENERAL DESCRIPTION
FEATURES
The ICS853016 is a low skew, high perfor- • (1) Differential 3.3V, 5V LVPECL / ECL output pair and
ICS
mance 1-to-2 Differential-to-3.3V, 5V LVPECL/
ECL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS853016
(1) Single-ended 3.3V, 5V LVPECL / ECL output
HiPerClockS™
• (1) Differential D, nD input pair
• D, nD pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
is characterized to operate from either a 3.3V or a 5V
power supply. Guaranteed duty cycle skew character-
istic makes the ICS853016 ideal for those clock distri-
bution applications demanding well defined perfor-
mance and repeatability.
• Output frequency: >3GHz (typical)
• Translates any single ended input signal to 3.3V to 5V
LVPECL levels with resistor bias on nD input
• Duty cycle skew: 10ps (typical)
• Propagation delay: 400ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 3.0V to 5.5V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -5.5V to -3.0V
• -40°C to 85°C ambient operating temperature
• Pin compatible with MC100EP16VCD and MC100EP16VCDT
BLOCK DIAGRAM
PIN ASSIGNMENT
nQ
D
VBB/nD
Vcc
QHG
nQHG
VEE
1
2
3
4
8
7
6
5
nQ
VCC
nEN
ICS853016
8-Lead SOIC
D
QHG
3.90mm x 4.90mm x 1.37mm package body
M Package
TopView
ICS853016
8-LeadTSSOP, 118mil
3mm x 3mm x 0.95mm package body
G Package
VBB/nD
nQHG
OE
VBB
LEN
Q
TopView
LATCH
nEN
VEE
D
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853016AM
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REV. A NOVEMBER 30, 2004
1
PRELIMINARY
ICS853016
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
D
IFFERENTIAL
-
TO-3.3V, 5V LVPECL/ECL FANOUT
B
UFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
nQ
Type
Description
Single-ended clock output. LVPECL interface levels.
1
2
Output
Input
D
Pulldown Non-inverting differential clock input. LVPECL interface levels.
Reference voltage output/Inverting differential clock input.
LVPECL interface levels.
3
VBB/nD
Input
4
5
nEN
VEE
Input
Power
Output
Power
Pulldown Enable input. Default LOW when left open. LVCMOS/LVTTL interface levels.
Negative supply pin.
6, 7
8
nQHG, QHG
VCC
Differential clock outputs. LVPECL interface levels.
Positive supply pin.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
RPULLDOWN Input Pulldown Resistor
75
KΩ
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REV. A NOVEMBER 30, 2004
2
PRELIMINARY
ICS853016
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
D
IFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT
B
UFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
-6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5V
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
VBB Sink/Source, IBB
0.5mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature,TSTG -65°C to 150°C
PackageThermal Impedance, θJA 112.7°C/W (0 lfpm)
(Junction-to-Ambient) for 8 Lead SOIC
PackageThermal Impedance, θJA 101.7°C/W (0 m/s)
(Junction-to-Ambient) for 8 Lead TSSOP
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.0V TO 5.5V;VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
3.3
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
3.0
5.5
V
30
mA
TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
-40°C
25°C
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
Min
Typ
Max
Min
Max
2.175 2.275 2.38 2.225 2.295 2.37 2.295 2.33 2.365
1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63
V
V
V
V
V
VOH
VOL
VIH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage (Single-Ended)
Input Low Voltage (Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
2.075
1.43
1.86
150
2.36 2.075
1.765 1.43
2.36 2.075
1.765 1.43
2.36
1.765
1.98
VIL
1.98
1.86
150
1.98
1.86
150
VBB
VPP
800
1200
800
1200
800
1200
m
V
Input High Voltage
Common Mode Range; NOTE 3, 4
1.2
3.3
1.2
3.3
1.2
3.3
V
VCMR
150
150
150
µA
µA
IIH
IIL
Input High Current
Input Low Current
D
D
-10
-10
-10
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for D is VCC + 0.3V.
853016AM
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REV. A NOVEMBER 30, 2004
3
PRELIMINARY
ICS853016
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
D
IFFERENTIAL
-
TO-3.3V, 5V LVPECL/ECL FANOUT
B
UFFER
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 5.0V; VEE = 0V
-40°C
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
Min
Max
Min
Max
3.875 3.975 4.08 3.925 3.995 4.07 3.995 4.03 4.065
3.105 3.245 3.38 3.125 3.22 3.315 3.14 3.235 3.33
V
V
V
V
V
VOH
VOL
VIH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage (Single-Ended)
Input Low Voltage (Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
3.775
3.13
3.56
150
4.06 3.775
3.465 3.13
4.06 3.775
3.465 3.13
4.06
3.465
3.68
VIL
3.68
3.56
150
3.68
3.56
150
VBB
VPP
800
1200
800
1200
800
1200
m
V
Input High Voltage
Common Mode Range; NOTE 3, 4
1.2
5
1.2
5
1.2
5
V
VCMR
150
150
150
µA
µA
IIH
IIL
Input High Current
Input Low Current
D
D
-10
-10
-10
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for D is VCC + 0.3V.
TABLE 3D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -3.0V
-40°C
Typ Max
25°C
Typ Max
85°C
Symbol Parameter
Units
Min
-1.125
-1.895
-1.225
-1.87
-1.44
150
Min
-1.075
-1.875
-1.225
-1.87
-1.44
150
Min
-1.005
-1.86
-1.225
-1.87
-1.44
150
Typ Max
-1.025
-1.755
-0.92
-1.62
-0.94
-1.535
-1.32
1200
-1.005
-1.78
-0.93
-1.685
-0.94
-1.535
-1.32
1200
-0.97
-0.935
-1.67
-0.94
-1.535
-1.32
1200
V
V
V
V
V
VOH
VOL
VIH
Output High Voltage; NOTE 1
-1.765
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
VIL
VBB
VPP
800
800
800
mV
Input High Voltage
Common Mode Range; NOTE 3, 4
VEE+1.2V
0
VEE+1.2V
0
VEE+1.2V
0
V
VCMR
150
150
150
µA
µA
IIH
IIL
Input High Current
Input Low Current
D
D
-10
-10
-10
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for D is VCC + 0.3V.
853016AM
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REV. A NOVEMBER 30, 2004
4
PRELIMINARY
ICS853016
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
D
IFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT
B
UFFER
TABLE 4. AC CHARACTERISTICS, VCC = 0V;VEE = -5.5V TO -3.0V OR VCC = 3.0V TO 5.5V;VEE = 0V
-40°C 25°C
Min Typ Max Min Typ
85°C
Symbol Parameter
Units
Max Min Typ Max
fMAX
Output Frequency
TBD
TBD
TBD
TBD
TBD
TBD
TBD
>3
350
400
400
450
10
TBD
TBD
TBD
TBD
TBD
TBD
TBD
GHz
ps
(Differential) nQ
Propagation
Delay;
NOTE 1
(Differential) QHG, nQHG
(Single-Ended) nQ
ps
tPLH
tPHL
ps
(Single-Ended) QHG, nQHG
ps
tsk(odc) Duty Cycle Skew; NOTE 2, 3
ps
Output Rise/
Fall Time
20% to 80%
nQ
HG, nQHG
300
ps
tR/tF
Q
TBD
150
TBD
ps
All parameters are measured at f ≤ 1.7GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured for only differential operation from the cross point of the inputs to the cross point of the outputs.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
853016AM
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REV. A NOVEMBER 30, 2004
5
PRELIMINARY
ICS853016
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-3.3V, 5V LVPECL/ECL FANOUT
B
UFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nQHG
LVPECL
VEE
VPP
VCMR
Cross Points
QHG
nQx
VEE
-3.5V to -1.0V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nD
D
80%
tF
80%
VSWING
20%
Clock
20%
nQ
Outputs
tR
nQHG
QHG
tpLH
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
Part 1
nQHG
QHG
Part 2
nQHG
QHG
tsk(odc)
DUTY CYCLE SKEW
853016AM
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REV. A NOVEMBER 30, 2004
6
PRELIMINARY
ICS853016
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
D
IFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT
B
UFFER
APPLICATION INFORMATION
WIRING THE INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 1 shows an example of the input that can be wired to
accept single ended LVPECL levels.
VCC
C1
0.1u
CLK_IN
D
VBB/nD
FIGURE 1. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A NOVEMBER 30, 2004
7
PRELIMINARY
ICS853016
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
D
IFFERENTIAL
-
TO-3.3V, 5V LVPECL/ECL FANOUT
B
UFFER
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
TERMINATION FOR 5V LVPECL OUTPUT
This section shows examples of 5V LVPECL output termina- VCC - 2V = 3V at the receiver.Figure 3B showsThevenin equiva-
tion.Figure 3A shows standard termination for 5V LVPECL.The
lence of Figure 3A. In actual application where the 3V DC power
termination requires matched load of 50Ω resistors pull down to
supply is not available, this approached is normally used.
5V
5V
5V
5V
R3
84
R4
84
PECL
Zo = 50 Ohm
Zo = 50 Ohm
PECL
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
PECL
PECL
R1
125
R2
125
R1
50
R2
50
3V
FIGURE 3A. STANDARD 5V PECL OUTPUT TERMINATION
FIGURE 3B. 5V PECL OUTPUT TERMINATION EXAMPLE
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REV. A NOVEMBER 30, 2004
8
PRELIMINARY
ICS853016
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
D
IFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT
B
UFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853016.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853016 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 5.5V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 5.5V * 30mA = 165mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW
Total Power_MAX (3.8V, with all outputs switching) = 165mW + 61.88mW = 226.88mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W perTable 5A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.227W * 103.3°C/W = 108.4°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 5A. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 5B. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
853016AM
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REV. A NOVEMBER 30, 2004
9
PRELIMINARY
ICS853016
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
D
IFFERENTIAL
-
TO-3.3V, 5V LVPECL/ECL FANOUT
B
UFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.935V
OH_MAX
CC_MAX
)
= 0.935V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.67V
OL_MAX
CC_MAX
)
(V
- V
= 1.67V
CCO_MAX
OL_MAX
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC _MAX
OH_MAX
L
CC
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
853016AM
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REV. A NOVEMBER 30, 2004
10
PRELIMINARY
ICS853016
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
D
IFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT
B
UFFER
RELIABILITY INFORMATION
TABLE 6A. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC StandardTest Boards
Multi-Layer PCB, JEDEC StandardTest Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 6B. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
TRANSISTOR COUNT
The transistor count for ICS853016 is: 163
853016AM
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REV. A NOVEMBER 30, 2004
11
PRELIMINARY
ICS853016
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
D
IFFERENTIAL
-
TO-3.3V, 5V LVPECL/ECL FANOUT
B
UFFER
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 7A. PACKAGE DIMENSIONS
TABLE 7B. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Millimeters
SYMBOL
Minimum
Maximum
MINIMUN
MAXIMUM
N
A
8
N
A
A1
B
C
D
E
e
8
--
1.10
0.15
0.97
0.38
0.23
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
A1
A2
b
0
0.79
0.22
0.08
c
D
3.00 BASIC
4.90 BASIC
3.00 BASIC
0.65 BASIC
1.95 BASIC
E
1.27 BASIC
E1
e
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
e1
L
L
0.40
0°
0.80
8°
α
α
Reference Document: JEDEC Publication 95, MS-012
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-187
853016AM
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REV. A NOVEMBER 30, 2004
12
PRELIMINARY
ICS853016
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
D
IFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT
B
UFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS853016AM
Marking
853016A
Package
Count
96 per tube
2500
Temperature
-40°C to 85°C
-40°C to 85°C
8 lead SOIC
ICS853016AMT
ICS853016AG
853016A
016A
8 lead SOIC on Tape and Reel
8 lead TSSOP
100 per tube -40°C to 85°C
2500 -40°C to 85°C
ICS853016AGT
016A
8 lead TSSOP on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853016AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
13
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