ICS853058AG [ICSI]
8:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER; 8 ： 1 ，差分至3.3V或2.5V LVPECL / ECL时钟多路复用器
| 型号： | ICS853058AG |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 8:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER |
| 文件： | 总15页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS853058
Integrated
Circuit
Systems, Inc.
8:1, DIFFERENTIAL
- -
TO
3.3V OR 2.5V LVPECL/ECL CLOCK
MULTIPLEXER
GENERAL DESCRIPTION
FEATURES
The ICS853058 is an 8:1 Differential-to-3.3V or • High speed 8:1 differential multiplexer
ICS
2.5V LVPECL / ECL Clock Multiplexer which can
• 1 differential 3.3V or 2.5V LVPECL output
HiPerClockS™
operate up to 2.5GHz and is a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS853058 has 8 differ-
• 8 selectable differential PCLK, nPCLK inputs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
ential selectable clock inputs. The PCLK, nPCLK input pairs
can accept LVPECL, LVDS, CML or SSTL levels.The fully dif-
ferential architecture and low propagation delay make it ideal
for use in clock distribution circuits.The select pins have inter-
nal pulldown resistors.The SEL2 pin is the most significant bit
and the binary number applied to the select pins will select the
same numbered data input (i.e., 000 selects PCLK0, nPCLK0).
• Maximum output frequency: 2.5GHz
• Translates any single ended input signal to
LVPECL levels with resistor bias on nPCLKx input
• Part-to-part skew: TBD
• Propagation delay: 620ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -2.375V
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
24
23 nPCLK7
PLCK6
21 nPCLK6
PCLK0
nPCLK0
PCLK1
nPCLK1
VCC
SEL0
SEL1
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
PCLK7
PCLK0
000
22
nPCLK0
20
19
18
17
16
15
14
13
VCC
PCLK1
001
Q0
nPCLK1
nQ0
VEE
PCLK2
010
PCLK5
nPCLK5
PCLK4
nPCLK4
9
nPCLK2
10
11
12
PCLK3
011
nPCLK3
Q0
nQ0
PCLK4
100
ICS853058
24-Lead, 173-MIL TSSOP
4.4mm x 7.8mm x 0.92mm body package
G Package
nPCLK4
PCLK5
101
nPCLK5
Top View
PCLK6
110
nPCLK6
PCLK7
111
nPCLK7
SEL0
SEL1
SEL2
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
1
PRELIMINARY
ICS853058
Integrated
Circuit
Systems, Inc.
8:1, DIFFERENTIAL
- -
TO
3.3V OR 2.5V LVPECL/ECL CLOCK
MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
PCLK0
Input
Input
Input
Input
Pulldown
Pullup/Pulldown
Pulldown
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
2
3
4
nPCLK0
PCLK1
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
nPCLK1
Pullup/Pulldown
5, 20
6, 7, 8
9
VCC
Power
Input
Input
Positive supply pins.
SEL0, SEL1, SEL2
PCLK2
Pulldown
Pulldown
Clock select input pins. LVCMOS/LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
10
11
12
nPCLK2
PCLK3
Input
Input
Input
Pullup/Pulldown
Pulldown
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
nPCLK3
Pullup/Pulldown
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
13
14
15
nPCLK4
PCLK4
Input
Input
Input
Pullup/Pulldown
Pulldown
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
nPCLK5
Pullup/Pulldown
Pulldown
16
17
PCLK5
VEE
Input
Power
Output
Non-inverting differential LVPECL clock input.
Negative supply pin.
18, 19
nQ0, Q0
Differential output pair. LVPECL interface levels.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
21
22
23
24
nPCLK6
PCLK6
nPCLK7
PCLK7
Input
Input
Input
Input
Pullup/Pulldown
Pulldown
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
Pullup/Pulldown
Pulldown
Non-inverting differential LVPECL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
2
PRELIMINARY
ICS853058
Integrated
Circuit
Systems, Inc.
8:1, DIFFERENTIAL
- -
TO
3.3V OR 2.5V LVPECL/ECL CLOCK
MULTIPLEXER
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
RPULLDOWN Input Pulldown Resistor
75
50
KΩ
KΩ
RVDD/2
Pullup/Pulldown Resistosr
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
SEL2
SEL1
SEL0
Q0
nQ0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
PCLK7
nPCLK0
nPCLK1
nPCLK2
nPCLK3
nPCLK4
nPCLK5
nPCLK6
nPCLK7
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
3
PRELIMINARY
ICS853058
Integrated
Circuit
Systems, Inc.
8:1, DIFFERENTIAL
- -
TO
3.3V OR 2.5V LVPECL/ECL CLOCK
MULTIPLEXER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
4.6V (LVPECL mode, VEE = 0)
-4.6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5V
Negative Supply Voltage,VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
OperatingTemperature Range,TA -40°C to +85°C
StorageTemperature,TSTG -65°C to 150°C
PackageThermal Impedance, θJA 70°C/W (0 mps)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
3.3
Maximum Units
VCC
ICC
Positive Supply Voltage
Power Supply Current
2.375
3.465
V
38
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
Input High Voltage SEL0:SEL2
2
VCC + 0.3
0.8
V
V
Input Low Voltage SEL0:SEL2
-0.3
VCC = VIN = 3.465V,
IIH
IIL
Input High Current SEL0:SEL2
150
µA
µA
V
CC = VIN = 2.625V
CC = 3.465V, VIN = 0V,
VCC = 2.625V, VIN = 0V
V
Input Low Current SEL0:SEL2
-150
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol Parameter Test Conditions
IIH Input High Current
Minimum
Typical
Maximum Units
PCLK0:PCLK7
nPCLK0:nPCLK7
V
CC = VIN = 3.465V
150
µA
PCLK0:PCLK7
V
CC = 3.465V, VIN = 0V
CC = 3.465V, VIN = 0V
-10
-150
0.15
µA
µA
V
IIL
Input Low Current
nPCLK0:nPCLK7
V
VPP
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
NOTE 1, 2
VCMR
1.2
3.3
V
VOH
Output High Voltage Voltage; NOTE 3
Output Low Voltage; NOTE 3
VCC - 1.005
VCC - 1.78
0.8
V
V
V
VOL
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCC - 2V.
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
4
PRELIMINARY
ICS853058
Integrated
Circuit
Systems, Inc.
8:1, DIFFERENTIAL
- -
TO
3.3V OR 2.5V LVPECL/ECL CLOCK
MULTIPLEXER
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.465V TO -2.375V
Symbol Parameter Test Conditions
Minimum
Typical
-1.005
-1.78
Maximum Units
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
V
V
Output Low Voltage; NOTE 1
Input High Voltage
-1.225
-1.87
-0.94
V
V
Input Low Voltage
-1.535
VPP
Peak-to-Peak Input Voltage
800
mV
Input High Voltage
Common Mode Range; NOTE 2, 3
VCMR
IIH
VEE + 1.2
0
V
Input
PCLK0:PCLK7
150
µA
High Current nPCLK0:nPCLK7
PCLK0:PCLK7
-10
µA
µA
Input Low
Current
IIL
nPCLK0:nPCLK7
-150
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.465V TO -2.375V OR VCC = 2.375 TO 3.465V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
2.5
GHz
ps
tPD
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time
620
TBD
150
tsk(pp)
tR / tF
ps
20% to 80%
ps
All parameters measured up to 1.3GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
5
PRELIMINARY
ICS853058
Integrated
Circuit
Systems, Inc.
8:1, DIFFERENTIAL
- -
TO
3.3V OR 2.5V LVPECL/ECL CLOCK
MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nPCLK0:7
VPP
VCMR
LVPECL
Cross Points
PCLK0:7
VEE
nQx
VEE
-1.465V to -0.375V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nPCLK0:7
PCLK0:7
nQ0
nQx
PART 1
Qx
nQy
PART 2
Qy
Q0
tPD
tsk(pp)
PROPAGATION DELAY
PART-TO-PART SKEW
80%
tF
80%
VOD
Clock
20%
20%
Outputs
tR
OUTPUT RISE/FALL TIME
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
6
PRELIMINARY
ICS853058
Integrated
Circuit
Systems, Inc.
8:1, DIFFERENTIAL
- -
TO
3.3V OR 2.5V LVPECL/ECL CLOCK
APPLICATION INFORMATION
MULTIPLEXER
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VCC/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVCC= 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
PCLK
V_REF
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- 50Ω transmission lines. Matched impedance techniques should
tion for LVPECL outputs.The two different layouts mentioned be used to maximize operating frequency and minimize signal
are recommended only as guidelines.
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
7
PRELIMINARY
ICS853058
Integrated
Circuit
Systems, Inc.
8:1, DIFFERENTIAL
- -
TO
3.3V OR 2.5V LVPECL/ECL CLOCK
MULTIPLEXER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V ground level. The R3 in Figure 3B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 3C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driver
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
8
PRELIMINARY
ICS853058
Integrated
Circuit
Systems, Inc.
8:1, DIFFERENTIAL
- -
TO
3.3V OR 2.5V LVPECL/ECL CLOCK
MULTIPLEXER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other gested here are examples only. If the driver is from another
differential signals. Both VSWING and VOH must meet the VPP vendor, use their termination recommendation. Please con-
and VCMR input requirements. Figures 4A to 4E show inter- sult with the vendor of the driver component to confirm the
face examples for the HiPerClockS PCLK/nPCLK input driven driver termination requirements.
by the most common driver types. The input interfaces sug-
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
nPCLK
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL IN DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
R3
1K
R4
1K
Zo = 50 Ohm
Zo = 50 Ohm
C1
C2
LVDS
PCLK
PCLK
R5
100
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
9
PRELIMINARY
ICS853058
Integrated
Circuit
Systems, Inc.
8:1, DIFFERENTIAL
- -
TO
3.3V OR 2.5V LVPECL/ECL CLOCK
MULTIPLEXER
SCHEMATIC EXAMPLE
An application schematic example of ICS853058 is shown in nation approaches are available in the LVPECL Termination
Application Note. It is recommended at least one decoupling ca-
pacitor per power pin.The decoupling capacitor should be low
Figure 5.The inputs can accept various types of differential sig-
nals. In this example, the inputs are driven by 3.3V LVPECL
drivers.The ICS853058 output is an LVPECL driver.An example ESR and located as close as possible to the power pin.
of LVPECL terminations is shown this schematic. Other termi-
Zo = 50
Logic Control Input Examples
Set Logic
Input to
'1'
Set Logic
Input to
'0'
Zo = 50
3.3V
3.3V
LVPECL
R1
50
R2
50
RU1
1K
RU2
Not Install
To Logic
Input
pins
To Logic
Input
pins
R3
50
RD1
Not Install
RD2
1K
Zo = 50
U1
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
PCLK0
nPCLK0
PCLK1
nPCLK1
VCC
SEL0
SEL1
PCLK7
nPCLK7
PCLK6
nPCLK6
VCC
Q0
nQ0
GND
PCLK5
nPCLK5
PCLK4
nPCLK4
Zo = 50
Zo = 50
3.3V
3.3V
+
-
LVPECL
R4
50
R5
50
Zo = 50
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
10
11
12
LVPECL
R6
50
C2
0.1u
R7
50
R8
50
C1
0.1u
ICS853058
R9
50
FIGURE 5. ICS853058 SCHEMATIC EXAMPLE
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
10
PRELIMINARY
ICS853058
Integrated
Circuit
Systems, Inc.
8:1, DIFFERENTIAL
- -
TO
3.3V OR 2.5V LVPECL/ECL CLOCK
MULTIPLEXER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853058.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853058 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 38mA = 131.67mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 1 * 30.94mW = 30.94mW
Total Power_MAX (3.465V, with all outputs switching) = 131.67mW + 30.94mW = 162.61mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.163W * 65°C/W = 95.6°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP FORCED CONVECTION
θJA byVelocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
11
PRELIMINARY
ICS853058
Integrated
Circuit
Systems, Inc.
8:1, DIFFERENTIAL
- -
TO
3.3V OR 2.5V LVPECL/ECL CLOCK
MULTIPLEXER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.935V
OH_MAX
CCO_MAX
)
= 0.935V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.67V
OL_MAX
CCO_MAX
)
= 1.67V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
12
PRELIMINARY
ICS853058
Integrated
Circuit
Systems, Inc.
8:1, DIFFERENTIAL
- -
TO
3.3V OR 2.5V LVPECL/ECL CLOCK
MULTIPLEXER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS853058 is: 326
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
13
PRELIMINARY
ICS853058
Integrated
Circuit
Systems, Inc.
8:1, DIFFERENTIAL
- -
TO
3.3V OR 2.5V LVPECL/ECL CLOCK
MULTIPLEXER
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MS-153
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
14
PRELIMINARY
ICS853058
Integrated
Circuit
Systems, Inc.
8:1, DIFFERENTIAL
- -
TO
3.3V OR 2.5V LVPECL/ECL CLOCK
MULTIPLEXER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
60 per tube
2500
Temperature
-40°C to 85°C
-40°C to 85°C
ICS853058AG
ICS853058AGT
ICS853058AG
ICS853058AG
24 Lead TSSOP
24 Lead TSSOP on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 13, 2004
15
相关型号：
ICS853058AGLE
Multiplexer, 853058 Series, 1-Func, 8 Line Input, 1 Line Output, Complementary Output, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MS-153, TSSOP-24
IDT
ICS853058AGLET
Multiplexer, 853058 Series, 1-Func, 8 Line Input, 1 Line Output, Complementary Output, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MS-153, TSSOP-24
IDT
ICS853058AGLF
Multiplexer, 853058 Series, 1-Func, 8 Line Input, 1 Line Output, Complementary Output, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MS-153, TSSOP-24
IDT
ICS8530DY-01LF
Low Skew Clock Driver, 8530 Series, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, LQFP-48
IDT
ICS8530DY-01LFT
Low Skew Clock Driver, 8530 Series, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, LQFP-48
IDT
ICS8530DYI-01LF
Low Skew Clock Driver, 8530 Series, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1 MM HEIGHT, MS-026, TQFP-48
IDT
ICS8530DYI-01LFT
Low Skew Clock Driver, 8530 Series, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1 MM HEIGHT, MS-026, TQFP-48
IDT
©2020 ICPDF网 联系我们和版权申明