ICS85310AYI-01 [ICSI]
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER; 低偏移， 1到10差分至2.5V / 3.3V ECL / LVPECL扇出缓冲器
| 型号： | ICS85310AYI-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER |
| 文件： | 总15页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS85310I-01 is a low skew, high perfor- • Ten differential 2.5V/3.3V LVPECL / ECL outputs
ICS
HiPerClockS™
mance 1-to-10 Differential-to-2.5V/3.3V ECL/
• Two selectable differential input pairs
LVPECL Fanout Buffer and a member of the
HiPerClockS™family of High Performance
Clock Solutions from ICS. The CLKx, nCLKx
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
pairs can accept most standard differential input levels. The
ICS85310I-01 is characterized to operate from either a
2.5V or a 3.3V power supply. Guaranteed output and part-
to-part skew characteristics make the ICS85310I-01 ideal
for those clock distribution applications demanding well
defined performance and repeatability.
• Maximum output frequency: 700MHz
• Translates any single ended input signal to
3.3V LVPECL levels with resistor bias on nCLK input
• Output skew: 30ps (typical)
• Part-to-part skew: 140ps (typical)
• Propagation delay: 2ns (typical)
• Additive phase jitter, RMS: <0.13ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
CLK0
nCLK0
0
1
CLK1
nCLK1
Q1
nQ1
32 31 30 29 28 27 26 25
Q2
nQ2
VCC
CLK_SEL
CLK0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q3
CLK_SEL
nQ3
Q4
Q3
nQ3
nCLK0
nc
nQ4
Q5
Q4
nQ4
ICS85310I-01
CLK1
nQ5
Q6
Q5
nQ5
nCLK1
nQ6
VEE
Q6
nQ6
9
10 11 12 13 14 15 16
Q7
nQ7
Q8
nQ8
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
TopView
Q9
nQ9
85310AYI-01
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REV.F JANUARY16, 2006
1
ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VCC
Power
Input
Positive supply pin.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.
2
CLK_SEL
Pulldown
3
4
CLK0
nCLK0
nc
Input
Input
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
No connect.
5
Unused
Input
6
CLK1
Pulldown Non-inverting differential clock input.
7
nCLK1
VEE
Input
Pullup
Inverting differential clock input.
8
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Negative supply pin.
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
VCCO
Output supply pins.
nQ9, Q9
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
nQ1, Q1 Output
nQ0, Q0 Output
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
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2
ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
47.9°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
3.3
Maximum Units
VCC
VCCO
IEE
Positive Supply Voltage
3.8
3.8
120
V
V
Output Supply Voltage
Power Supply Current
2.375
3.3
mA
Table 3B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 2.375V to 3.8V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
Input Low Voltage
CLK_SEL
CLK_SEL
2
-0.3
-5
VCC + 0.3
0.8
V
V
Input High Current CLK_SEL
Input Low Current CLK_SEL
VCC = VIN = 3.8V
µA
µA
IIL
VCC = 3.8V, VIN = 0V
150
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum
Typical
Maximum Units
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
V
CC = VIN = 3.8V
CC = VIN = 3.8V
150
5
µA
µA
µA
µA
V
V
V
CC = 3.8V, VIN = 0V
CC = 3.8V, VIN = 0V
-5
-150
IIL
Input Low Current
nCLK0, nCLK1
V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VCC + 0.3V.
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REV.F JANUARY16, 2006
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ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC, VCCO = 2.375V TO 3.8V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VCCO - 1.4
Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.0
VCCO - 1.7
0.85
V
V
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VSWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 4. AC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
700
2.5
55
MHz
ns
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
IJ 500MHz
2
tsk(o)
tsk(pp)
30
ps
Part-to-Part Skew; NOTE 3, 4
140
340
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
tjit
<0.13
ps
tR
Output Rise Time
Output Fall Time
Output Duty Cycle
20% to 80%
20% to 80%
200
200
47
700
700
53
ps
ps
%
tF
odc
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV.F JANUARY16, 2006
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ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
Additive Phase Jitter, RMS
@ 155.52MHz = <0.13ps typical
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
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REV.F JANUARY16, 2006
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ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
,
Qx
VCCO
nCLK0, nCLK1
VPP
LVPECL
VCMR
Cross Points
CLK0, CLK1
nQx
VEE
VEE
-0.375V to -1.8V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK0,
nCLK1
80%
tF
80%
CLK0,
CLK1
VSWING
20%
nQ0:nQ9
Clock
20%
Outputs
tR
Q0:Q9
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0:nQ9
Q0:Q9
tPW
tPERIOD
tPW
odc =
x 100%
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV.F JANUARY16, 2006
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ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF ~ VCC/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
INPUTS:
LVPECL OUTPUT
CLK/nCLK INPUT:
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
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REV.F JANUARY16, 2006
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ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals.BothVSWING andVOH must meet the
VPP and VCMR input requirements. Figures 2A to 2E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types.The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 2A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 3A and
3B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched imped-
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUTT ERMINATION
FIGURE 3B. LVPECL OUTPUTTERMINATION
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REV.F JANUARY16, 2006
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ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85310I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85310I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 120mA = 456mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30.2mW = 302mW
Total Power_MAX (3.8V, with all outputs switching) = 456mW + 302mW = 758mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W perTable 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.758W * 42.1°C/W = 117°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θ
by Velocity (Linear Feet per Minute)
0
JA
200
55.9°C/W
500
50.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 1.0V
OH_MAX
CCO_MAX
)
= 1.0V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
CCO
OH_MAX
CCO _MAX
OH_MAX
L
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
CCO
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θ byVelocity (Linear Feet per Minute)
JA
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85310I-01 is: 1034
Pin compatible with MC100LVEP111
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ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
85310AYI-01
www.icst.com/products/hiperclocks.html
REV.F JANUARY16, 2006
13
ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS85310AYI-01
Marking
Package
Shipping Packaging Temperature
ICS85310AYI01
ICS85310AYI01
ICS5310AI01L
ICS5310AI01L
ICS5310AI01N
ICS5310AI01N
32 lead LQFP
tray
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS85310AYI-01T
ICS85310AYI-01LF
ICS85310AYI-01LFT
ICS85310AYI-01LN
ICS85310AYI-01LNT
32 lead LQFP
1000 tape & reel
tray
32 lead "Lead Free" LQFP
32 lead "Lead Free" LQFP
32 lead (Lead Free/Annealed) LQFP
32 lead (Lead Free/Annealed) LQFP
1000 tape & reel
tray
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
85310AYI-01
www.icst.com/products/hiperclocks.html
REV.F JANUARY16, 2006
14
ICS85310I-01
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Rev
B
Table
Page
Description of Change
AC Characterisitics table - tPD row, revised value from 2.25ns Max. to
2.5ns Max.
Date
T4
4
4/29/02
5/29/02
B
8
4
Added Termination for LVPECL Outputs.
T3D
Added LVPECL DC Characterisitics table.
C
D
Changed part number from ICS85310-01 to ICS85310I-01 in title and all
subsequent areas throughout the datasheet.
Power Supply table - increased max. value for IEE to 120mA from 30mA max.
7/26/02
T3A
T2
3
7
2
3
6
10/22/02
Power Considerations have re-adjusted to the increased IEE value.
Pin Characteristics - changed CIN 4pF max. to 4pF typical.
Absolute Maximum Ratings - updated Outputs.
Updated Single Ended Signal Driving Differential Input Drawing and LVPECL
Output Termination Drawings.
E
6/14/04
7
Added Differential Clock Input Interface section.
12
1
5
Added Lead Free/Annealed part number.
Features Section - added Additive Phase Jitter bullet.
Added Additive Phase Jitter Section.
F
F
6/22/05
1/16/06
T8
T8
13
7
14
Ordering Information Table - added Lead-Free Note.
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free part number and marking.
85310AYI-01
www.icst.com/products/hiperclocks.html
REV.F JANUARY16, 2006
15
相关型号：
ICS85310AYI-21
Low Skew Clock Driver, 85310 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32
IDT
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