ICS8534-01 [ICSI]
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER; 低偏移， 1到22差分至3.3V的LVPECL扇出缓冲器
| 型号： | ICS8534-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER |
| 文件： | 总17页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8534-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8534-01 is a low skew, 1-to-22 Differen- • 22 differential LVPECL outputs
ICS
tial-to-3.3V LVPECL Fanout Buffer and a member
• Selectable differential CLK, nCLK or LVPECL clock inputs
HiPerClockS™
of the HiPerClockS™Family of High Performance
Clock Solutions from ICS.The ICS8534-01 has two
selectable clock inputs. The CLK, nCLK pair can
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
accept most standard differential input levels.The PCLK, nPCLK
pair can accept LVPECL, CML, or SSTL input levels. The de-
vice is internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the OE
pin. The ICS8534-01’s low output and part-to-part skew char-
acteristics make it ideal for workstation, server, and other high
performance clock distribution applications.
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 500MHz
• Output skew: 100ps (maximum)
• Translates any single-ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
• Additive phase jitter, RMS: 0.04ps (typical)
• 3.3V supply mode
• 0°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
CLK
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCCO
Q14
VCCO
nQ6
Q6
0
1
nCLK
22
22
nQ14
Q15
Q0:Q21
nQ0:nQ21
nQ5
Q5
PCLK
nPCLK
nQ15
Q16
nQ4
Q4
LE
D
nQ16
Q17
Q
nQ3
Q3
ICS8534-01
OE
nQ17
Q18
nQ2
Q2
nQ18
Q19
nQ1
Q1
nQ19
Q20
nQ0
Q0
nQ20
VCCO
VCCO
1
2
3
4
5
6
7 8 9 10 11 12 13 14 15 16
64-LeadTQFP E-Pad
10mm x 10mm x 1.0mm package body
Y package
TopView
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REV. A NOVEMBER 19, 2004
1
ICS8534-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 16, 17, 32,
33, 48, 49, 64
VCCO
Power
Output supply pins.
2, 3, 12, 13
nc
VCC
CLK
Unused
Power
Input
No connect.
4
5
Core supply pin.
Pulldown Non-inverting differential clock input pair.
Pullup/
Pulldown
6
nCLK
Input
Inverting differential clock input pair. Pulled to 2/3 VCC.
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK inputs.
7
CLK_SEL
Input
Pullup
LVCMOS / LVTTL interface levels.
8
9
PCLK
nPCLK
VEE
Input
Input
Pulldown Non-inverting differential LVPECL clock input pair.
Pullup/
Pulldown
Inverting differential LVPECL clock input pair. Pulled to 2/3 VCC.
10
Power
Power supply ground.
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are disabled and drive differential low:
Qx = LOW, nQx = HIGH. LVCMOS / LVTTL interface levels.
11
OE
Input
Pullup
14, 15
18, 19
20, 21
22, 23
24, 25
26, 27
28, 29
30, 31
34, 35
36, 37
38, 39
40, 41
42, 43
44, 45
46, 47
50, 51
52, 53
54, 55
56, 57
58, 59
60, 61
62, 63
nQ21, Q21
nQ20, Q20
nQ19, Q19
nQ18, Q18
nQ17, Q17
nQ16, Q16
nQ15, Q15
nQ14, Q14
nQ13, Q13
nQ12, Q12
nQ11, Q11
nQ10, Q10
nQ9, Q9
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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REV. A NOVEMBER 19, 2004
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ICS8534-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
37
75
RPULLDOWN Input Pulldown Resistor
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
nQ0:nQ21
HIGH
OE
0
CLK_SEL
Q0:Q21
LOW
0
1
0
1
0
LOW
HIGH
1
CLK
nCLK
1
PCLK
nPCLK
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
OE
nQ0:nQ21
Q0:Q21
FIGURE 1. OE TIMING DIAGRAM
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ICS8534-01
Integrated
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LOW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
22.3°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V 5ꢀ, TA=0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC
VCCO
IEE
Core Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
230
V
V
Ouptut Power Supply Voltage
Power Supply Current
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V 5ꢀ, TA=0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VCC + 0.3
V
V
Input Low Voltage
-0.3
0.8
5
Input High Current OE, CLK_SEL
Input Low Current OE, CLK_SEL
µA
µA
IIL
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 3.3V 5ꢀ, TA=0°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
Minimum Typical Maximum Units
CLK
150
5
µA
µA
µA
µA
V
nCLK
CLK
-5
-150
IIL
Input Low Current
nCLK
VCC = 3.465V, VIN = 0V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK and nCLK is VCC + 0.3V.
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REV. A NOVEMBER 19, 2004
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ICS8534-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V 5ꢀ, TA=0°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
Minimum Typical Maximum Units
PCLK
150
5
µA
µA
µA
µA
V
nPCLK
PCLK
-5
-150
IIL
Input Low Current
nPCLK
VPP
Peak-to-Peak Input Voltage
0.3
1
VCC
VCMR
VOH
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
VEE + 1.5
VCC - 1.4
VCC - 2.0
0.6
V
VCC - 0.9
VCC -1.7
1.0
V
VOL
Output Low Voltage; NOTE 3
V
VSWING
Peak-to-Peak Output Voltage Swing
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V 5ꢀ, TA=0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
fMAX
Output Frequency
500
3.0
MHz
ns
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
f ≤ 500MHz
2.0
tsk(o)
tsk(pp)
100
700
ps
Part-to-Part Skew; NOTE 3, 5
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section;
NOTE 4
tjit
(12KHz to 20MHz)
20ꢀ to 80ꢀ
0.04
ps
tR / tF
tS
Output Rise/Fall Time
Setup Time
200
1.0
0.5
48
700
ps
ns
ns
ꢀ
tH
Hold Time
f ≤ 266MHz
52
54
odc
Output Duty Cycle
266 < f ≤ 500MHz
46
ꢀ
All parameters measured at fMAX unless noted otherwise.
Special thermal considerations may be required. See Applications Section.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions at the same temperature. Using the same type of inputs on each device,
the outputs are measured at the differential cross points.
NOTE 4: Driving only one input clock.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A NOVEMBER 19, 2004
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Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
Additive Phase Jitter, RMS
@ 156.25MHz (12KHz - 20MHz)
= 0.04ps (typical)
-50
-60
-70
-80
-90
-100
-110
-120
-130
140
-
-150
160
-
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
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REV. A NOVEMBER 19, 2004
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ICS8534-01
Integrated
Circuit
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LOW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
Qx
VCC
,
VCCO
nCLK, nPCLK
VPP
LVPECL
VCMR
Cross Points
nQx
CLK, PCLK
VEE
VEE
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
nQx
nQx
Qx
Qx
PART 2
nQy
nQy
Qy
nQy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK, nPCLK
CLK, PCLK
nQ0:nQ21
80ꢀ
80ꢀ
VSWING
20ꢀ
Clock
20ꢀ
Outputs
tF
tR
Q0:Q21
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0:nQ21
Q0:Q21
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS8534-01
Integrated
Circuit
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LOW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VCC/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- 50Ω transmission lines. Matched impedance techniques should
tion for LVPECL outputs.The two different layouts mentioned be used to maximize operating frequency and minimize signal
are recommended only as guidelines.
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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Integrated
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LOW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 4A to 4E show inter- For example in Figure 4A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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LOW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other here are examples only. If the driver is from another vendor,
differential signals. Both VSWING and VOH must meet the VPP use their termination recommendation. Please consult with
and VCMR input requirements. Figures 5A to 5F show interface the vendor of the driver component to confirm the driver ter-
examples for the HiPerClockS PCLK/nPCLK input driven by mination requirements.
the most common driver types.The input interfaces suggested
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
R2
50
Zo = 50 Ohm
Zo = 50 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
R1
100
nPCLK
nPCLK
HiPerClockS
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
CML Built-In Pullup
FIGURE 5A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 5B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
R3
84
R4
84
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84
R2
84
FIGURE 5C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
2.5V
3.3V
3.3V
3.3V
2.5V
Zo = 50 Ohm
R3
1K
R4
1K
R3
120
R4
120
C1
C2
LVDS
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
PCLK
PCLK
R5
100
nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
1K
R2
1K
R1
120
R2
120
FIGURE 5E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 5F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
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LOW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
T
HERMAL
R
ELEASE
P
ATH
The exposed metal pad provides heat transfer from the device tacted through solder as shown in Figure 6.For further informa-
to the P.C. board. The exposed metal pad is ground pad con- tion, please refer to the Application Note on Surface Mount As-
nected to ground plane through thermal via.The exposed pad sembly of Amkor’sThermally /Electrically Enhance Leadframe
on the device to the exposed metal pad on the PCB is con- Base Package, Amkor Technology.
EXPOSED PAD
SOLDER
SOLDER MASK
SIGNAL
TRACE
SIGNAL
TRACE
GROUND PLANE
Expose Metal Pad
(GROUND PAD)
THERMAL VIA
F
IGURE 6. P.C. BOARD FOR
E
XPOSED
P
AD
T
HERMAL
R
ELEASE
P
ATH
E
XAMPLE
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ICS8534-01
Integrated
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LOW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8534-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8534-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 230mA = 796.95mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 22 * 30mW = 660mW
Total Power_MAX (3.465V, with all outputs switching) = 797mW + 660mW = 1457mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 17.2°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.457W * 17.2°C/W = 110.1°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 64-PIN TQFP, E-PAD, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
22.3°C/W
17.2°C/W
15.1°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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LOW
SKEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS8534-01
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LOW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 64 LEAD TQFP, E-PAD
θJA byVelocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
22.3°C/W
17.2°C/W
15.1°C/W
TRANSISTOR COUNT
The transistor count for ICS8534-01 is: 1474
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LOW
SKEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 64 LEAD TQFP, E-PAD
-HD VERSION
HEAT SLUG DOWN
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
ACD-HD
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
64
A
--
--
1.20
0.15
1.05
0.27
0.20
A1
0.05
0.95
0.17
0.09
0.10
1.0
A2
b
0.22
c
--
D
12.00 BASIC
10.00 BASIC
7.50 Ref.
12.00 BASIC
10.00 BASIC
7.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
θ
0.45
0.75
--
0°
7°
ccc
--
2.0
--
0.08
10.0
D3 & E3
--
Reference Document: JEDEC Publication 95, MS-026
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REV. A NOVEMBER 19, 2004
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ICS8534-01
Integrated
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LOW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
160 per tray
500
Temperature
0°C to 85°C
0°C to 85°C
ICS8534AY-01
ICS8534AY-01T
ICS8534AY-01
ICS8534AY-01
64 lead TQFP, E-Pad
64 lead TQFP, E-Pad on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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REV. A NOVEMBER 19, 2004
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LOW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-3.3V LVPECL FANOUT
BUFFER
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
A
15
Updated Package Outline and Package Dimensions.
11/19/04
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REV. A NOVEMBER 19, 2004
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