ICS85411AMT [ICSI]
Low Skew, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER; 低偏移， 1到2差分至LVDS扇出缓冲器
| 型号： | ICS85411AMT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Low Skew, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER |
| 文件： | 总13页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85411
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVDS FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS85411 is a low skew, high performance • 2 differential LVDS outputs
ICS
1-to-2 Differential-to-LVDS Fanout Buffer and a
• 1 differential CLK, nCLK clock input
HiPerClockS™
member of the HiPerClockS™family of High
Performance Clock Solutions from ICS. The
CLK, nCLK pair can accept most standard differ-
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
ential input levels.The ICS85411 is characterized to oper-
ate from a 3.3V power supply. Guaranteed output and
part-to-part skew characteristics make the ICS85411
ideal for those clock distribution applications demand-
ing well defined performance and repeatability.
• Maximum output frequency: 650MHz
• Translates any single ended input signal to
LVDS levels with resistor bias on nCLK input
• Output skew: 20ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Additive phase jitter, RMS: 0.05ps (typical)
• Propagation delay: 2.5 ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
VDD
1
2
3
4
8
7
6
5
Q0
nQ0
CLK
nCLK
GND
CLK
nCLK
Q1
nQ1
nQ1
ICS85411
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
TopView
85411AM
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REV. B JUNE 16, 2004
1
ICS85411
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVDS FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Q0, nQ0
Q1, nQ1
GND
Type
Description
1, 2
3, 4
5
Output
Output
Power
Input
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Power supply ground.
6
nCLK
CLK
Pulldown Inverting differential clock input.
7
Input
Pullup
Non-inverting differential clock input.
Positive supply pin.
8
VDD
Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
85411AM
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REV. B JUNE 16, 2004
2
ICS85411
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVDS FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
PackageThermal Impedance, θ
112.7°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
IDD
Positive Supply Voltage
Power Supply Current
3.135
3.3
3.465
50
V
mA
TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VDD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
Minimum Typical Maximum Units
CLK
5
µA
µA
µA
µA
V
nCLK
CLK
150
V
-150
-5
IIL
Input Low Current
nCLK
VDD = 3.465V, VIN = 0V
VPP
Peak-to-Peak Input Voltage
0.15
0.5
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VDD - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
TABLE 3C. LVDS DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
VOD
∆ VOD
VOS
Differential Output Voltage
200
280
0
360
40
mV
mV
V
VOD Magnitude Change
Offset Voltage
1.125
-20
1.25
5
1.375
25
∆ VOS
IOFF
VOS Magnitude Change
Power Off Leakage
mV
µA
mA
mA
1
+20
-5
IOSD
Differential Output Short Circuit Current
Output Short Circuit Current
-3.5
-3.5
IOS
-5
VOH
VOL
Output High Voltage
Output Low Voltage
1.34
1.06
1.6
V
V
0.9
85411AM
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REV. B JUNE 16, 2004
3
ICS85411
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVDS FANOUT
BUFFER
TABLE 4. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
650
2.5
20
MHz
ns
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
1.5
tsk(o)
tsk(pp)
ps
Part-to-Part Skew; NOTE 3, 4
250
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
tjit
(12KHz to 20MHz)
0.05
ps
tR / tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
> 500MHz
≤ 500MHz
150
47
350
53
ps
ꢀ
ꢀ
odc
Output Duty Cycle
48
52
All parameters measured at IJ 650MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
85411AM
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REV. B JUNE 16, 2004
4
ICS85411
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVDS FANOUT
BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
Input/Output Additive Phase Jitter
@ 200MHz (12KHz to 20MHz)
= 0.05ps typical
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
500M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
85411AM
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REV. B JUNE 16, 2004
5
ICS85411
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVDS FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
VDD
3.3V
nCLK
SCOPE
Qx
VPP
VCMR
Cross Points
3.3V 5ꢀ
Power Supply
Float GND
LVDS
CLK
+
-
nQx
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
PART 2
Qy
nQy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK
CLK
80ꢀ
tF
80ꢀ
VOD
Clock
20ꢀ
20ꢀ
nQ0, nQ1
Outputs
tR
Q0, Q1
tPD
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
VDD
nQ0, nQ1
Q0, Q1
➤
out
Pulse Width
tPERIOD
LVDS
DC Input
100
V
OD/∆ VOD
➤
tPW
odc =
out
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
DIFFERENTIAL OUTPUT VOLTAGE SETUP
85411AM
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REV. B JUNE 16, 2004
6
ICS85411
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVDS FANOUT
BUFFER
VDD
out
out
➤
DC Input
LVDS
LVDS
VDD
VOS/∆ VOS
IOFF
➤
OFFSET VOLTAGE SETUP
POWER OFF LEAKAGE SETUP
VDD
VDD
out
out
out
IOS
DC Input
IOSD
LVDS
DC Input
LVDS
IOSB
out
OUTPUT SHORT CIRCUIT CURRENT SETUP
DIFFERENTIAL OUTPUT SHORT CIRCUIT CURRENT SETUP
85411AM
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REV. B JUNE 16, 2004
7
ICS85411
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVDS FANOUT
BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 2. In a 100Ω receiver input. For a multiple LVDS outputs buffer, if only
differential transmission line environment, LVDS drivers partial outputs are used, it is recommended to terminate
require a matched load termination of 100Ω across near the the un-used outputs.
3.3V
3.3V
LVDS
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
85411AM
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REV. B JUNE 16, 2004
8
ICS85411
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVDS FANOUT
BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals. BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3E show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
85411AM
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REV. B JUNE 16, 2004
9
ICS85411
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVDS FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 5. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85411 is: 636
85411AM
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REV. B JUNE 16, 2004
10
ICS85411
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVDS FANOUT
BUFFER
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 6. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MINIMUN
MAXIMUM
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
85411AM
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REV. B JUNE 16, 2004
11
ICS85411
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVDS FANOUT
BUFFER
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS85411AM
Marking
Package
Count
96 per tube
2500
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
85411AM
85411AM
8 lead SOIC
ICS85411AMT
8 lead SOIC on Tape and Reel
8 lead "Lead Free" SOIC
ICS85411AMLF
ICS85411AMLFT
85411AMLF
85411AMLF
96 per tube
2500
8 lead "Lead Free" SOIC on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
85411AM
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REV. B JUNE 16, 2004
12
ICS85411
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVDS FANOUT
BUFFER
REVISION HISTORY SHEET
Description of Change
Rev
B
Table
Page
Date
6/9/04
6/16/04
1
4
Features - added Additive Phase Jitter bullet.
AC Characteristics table - added tjit row.
Added Additive Phase Jitter Application Note
T4
T7
5
B
12
Ordering Information Table - added Lead Free Part Number.
85411AM
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REV. B JUNE 16, 2004
13
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